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authorJeff Law <law@redhat.com>1998-07-24 18:50:12 +0000
committerJeff Law <law@redhat.com>1998-07-24 18:50:12 +0000
commit6d254a2d5f8e5bd69e060d54d93df131ade92861 (patch)
tree12d5cef9d4f7a2a543e8fc55e7d09d4ac8b1f460 /sim/mn10300
parentdc82df78bb45f0aa22585e44847ff57449e26f7d (diff)
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* am33.igen (translate_xreg): New function. Use it as needed.
Diffstat (limited to 'sim/mn10300')
-rw-r--r--sim/mn10300/ChangeLog4
-rw-r--r--sim/mn10300/am33.igen63
2 files changed, 39 insertions, 28 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index 5b88b7c..290c8f8 100644
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,4 +1,8 @@
start-sanitize-am33
+Fri Jul 24 12:49:28 1998 Jeffrey A Law (law@cygnus.com)
+
+ * am33.igen (translate_xreg): New function. Use it as needed.
+
Thu Jul 23 10:05:28 1998 Jeffrey A Law (law@cygnus.com)
* am33.igen: Add some missing instructions.
diff --git a/sim/mn10300/am33.igen b/sim/mn10300/am33.igen
index 38b8c34..5c73ee6 100644
--- a/sim/mn10300/am33.igen
+++ b/sim/mn10300/am33.igen
@@ -19,6 +19,25 @@
return REG_E0 + rreg;
}
+:function:::int:translate_xreg:int xreg
+{
+ switch (xreg)
+ {
+ case 0:
+ return REG_SP;
+ case 1:
+ return REG_MDRQ;
+ case 2:
+ return REG_MCRH;
+ case 3:
+ return REG_MCRL;
+ case 4:
+ return REG_MCVF;
+ default:
+ abort ();
+ }
+}
+
// 1111 0000 0010 00An; mov USP,An
8.0xf0+4.0x2,00,2.AN0:D0m:::mov
"mov"
@@ -589,17 +608,13 @@
"mov"
*am33
{
- int dstreg;
+ int dstreg, srcreg;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
+ srcreg = translate_xreg (SD_, XRM2);
- if (XRM2 == 0)
- {
- State.regs[dstreg] = State.regs[REG_SP];
- }
- else
- abort ();
+ State.regs[dstreg] = State.regs[srcreg];
}
// 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
@@ -607,17 +622,13 @@
"mov"
*am33
{
- int srcreg;
+ int srcreg, dstreg;
PC = cia;
srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_xreg (SD_, XRN0);
- if (XRN0 == 0)
- {
- State.regs[REG_SP] = State.regs[srcreg];
- }
- else
- abort ();
+ State.regs[dstreg] = State.regs[srcreg];
}
// 1111 1001 0000 1001 Rm Rn; and Rm,Rn
@@ -1713,11 +1724,9 @@
int dstreg;
PC = cia;
+ dstreg = translate_xreg (SD_, XRN0);
- if (XRN0 == 0)
- State.regs[REG_SP] = IMM8;
- else
- abort ();
+ State.regs[dstreg] = IMM8;
}
// 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
@@ -3274,14 +3283,12 @@
"mov"
*am33
{
+ int dstreg;
+
PC = cia;
+ dstreg = translate_xreg (SD_, XRN0);
- if (XRN0 == 0)
- {
- State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
- }
- else
- abort ();
+ State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
}
// 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
@@ -4037,12 +4044,12 @@
"mov"
*am33
{
+ int dstreg;
+
PC = cia;
+ dstreg = translate_xreg (SD_, XRN0);
- if (XRN0 == 0)
- State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
- else
- abort ();
+ State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
}
// 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn