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AgeCommit message (Expand)AuthorFilesLines
2023-01-10sim: mips: move libsim.a creation to top-levelMike Frysinger3-53/+70
2023-01-10sim: modules: trigger generation from top-levelMike Frysinger1-0/+1
2023-01-04sim: mips: add multi source to built sourcesMike Frysinger1-0/+4
2023-01-02sim: build: move generated headers to built sourcesMike Frysinger1-0/+2
2023-01-01sim: replace -I$srcroot/bfd include with -I$srcrootMike Frysinger3-4/+4
2023-01-01sim: refresh copyright dates a bitMike Frysinger1-1/+1
2023-01-01Update copyright year range in header of all files managed by GDBJoel Brobecker22-22/+22
2022-12-27sim: mips: hoist "multi" igen rules up to common buildsMike Frysinger3-124/+103
2022-12-27sim: mips: hoist "m16" igen rules up to common buildsMike Frysinger3-82/+88
2022-12-27sim: mips: hoist "single" igen rules up to common buildsMike Frysinger3-48/+52
2022-12-27sim: mips: rename "igen" generation mode to "single"Mike Frysinger2-34/+34
2022-12-27sim: mips: hoist itable igen rules up to common buildsMike Frysinger2-35/+50
2022-12-27sim: mips: unify itable generation (a bit)Mike Frysinger2-34/+22
2022-12-27sim: mips: rename multi_flags to igen_itable_flagsMike Frysinger2-9/+9
2022-12-27sim: mips: drop unused micromips igen logicMike Frysinger2-155/+0
2022-12-25sim: mips: move distclean settings to common buildMike Frysinger2-4/+3
2022-12-25sim: smp: plumb igen flag down to all usersMike Frysinger2-6/+4
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-24sim: mips: clean up a bit after mips/configure removalMike Frysinger2-5/+3
2022-12-24sim: mips: move igen settings to top-level configureMike Frysinger4-3634/+278
2022-12-24sim: mips: namespace igen configure varsMike Frysinger3-209/+218
2022-12-24sim: mips: add igen recursive depMike Frysinger1-0/+3
2022-12-24sim: mips: drop unused ENGINE_ISSUE_POSTFIX_HOOKMike Frysinger2-8/+0
2022-12-24sim: igen: drop move-if-changed usageMike Frysinger1-178/+83
2022-12-22sim: move bfd.h include out of sim-main.hMike Frysinger1-1/+0
2022-12-22sim: mips: trim redundant igen settingsMike Frysinger2-18/+0
2022-12-22sim: mips: merge mips64* with existing multi-run buildMike Frysinger2-10/+4
2022-12-22sim: mips: merge mips64vr5000 with existing multi-run buildMike Frysinger2-8/+2
2022-12-22sim: mips: switch from SIM_ADDR to address_wordMike Frysinger2-31/+13
2022-12-22sim: mips: merge mips64vr4300 with existing multi-run buildMike Frysinger2-8/+2
2022-12-21sim: mips: match target on cpu settingsMike Frysinger2-26/+26
2022-12-21sim: mips: move fpu bitsize defines to top-level configureMike Frysinger5-69/+16
2022-12-21sim: mips: move bitsize defines to top-level configureMike Frysinger5-97/+18
2022-12-21sim: mips: move subtarget defines to top-level configureMike Frysinger4-41/+35
2022-12-21sim: mips: always resolve active bfd mach dynamicallyMike Frysinger3-106/+3
2022-12-21sim: build: hoist lists of hw devices upMike Frysinger2-2/+5
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger1-2/+0
2022-12-21sim: mips: invert sim_cpu storageMike Frysinger2-73/+90
2022-11-08sim: mips: call Unpredictable instead of setting bogus values [PR sim/29276]Mike Frysinger1-2/+2
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+25
2022-11-04sim: mips: simplify fpu configure logicMike Frysinger2-22/+14
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-4/+4
2022-10-31sim: reg: constify store helperMike Frysinger1-2/+2
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-15/+15
2022-10-23sim: mips/ppc/riscv: re-add AC_CANONICAL_SYSTEM [PR sim/29439]Mike Frysinger2-0/+162
2022-05-13sim: remove use of PTRAlan Modra1-2/+2
2022-02-21sim: gdbinit: hoist setup to common codeMike Frysinger1-9/+0
2022-02-04sim: mips: Add simulator support for mips32r6/mips64r6Faraz Shahbazker11-70/+2147
2022-02-04sim: Allow toggling of quiet NaN-bit semanticsFaraz Shahbazker3-3/+7
2022-01-06sim: mips: migrate to standard uintXX_t typesMike Frysinger17-1083/+1083
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