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AgeCommit message (Expand)AuthorFilesLines
2023-08-19sim regenAlan Modra10-171/+191
2023-08-19sim --enable-cgen-maintAlan Modra1-2/+2
2023-01-15sim: modules.c: fix generation after recent refactorsMike Frysinger1-0/+3
2023-01-14sim: common: move modules.c to source trackingMike Frysinger1-1/+2
2023-01-14sim: build: drop most recursive build depsMike Frysinger1-2/+1
2023-01-14sim: common: move libcommon.a objects to sourcesMike Frysinger1-2/+2
2023-01-11sim: build: drop subdir Makefile.in filesMike Frysinger1-21/+0
2023-01-10sim: move arch-specific file compilation of common/ files to top-levelMike Frysinger1-2/+2
2023-01-10sim: iq2000: move arch-specific file compilation to top-levelMike Frysinger1-3/+0
2023-01-10sim: build: drop support for creating libsim.a in subdirsMike Frysinger1-3/+0
2023-01-10sim: iq2000: move libsim.a creation to top-levelMike Frysinger2-8/+32
2023-01-10sim: modules: trigger generation from top-levelMike Frysinger1-0/+1
2023-01-02sim: build: move generated headers to built sourcesMike Frysinger1-1/+2
2023-01-02sim: iq2000: hoist cgen rules to top-levelMike Frysinger2-26/+11
2023-01-01sim: replace -I$srcroot/opcodes include with -I$srcrootMike Frysinger1-2/+2
2023-01-01sim: iq2000: drop unused cpu define logicMike Frysinger1-6/+0
2023-01-01Update copyright year range in header of all files managed by GDBJoel Brobecker15-15/+15
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-23sim: cgen: move symcat.h include to where it's usedMike Frysinger1-1/+0
2022-12-23sim: cgen: move cgen-types.h include to cgen-defs.hMike Frysinger1-1/+0
2022-12-22sim: use bfd_vma when reading start addr from bfd infoMike Frysinger1-1/+1
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger1-2/+0
2022-12-21sim: iq2000: invert sim_cpu storageMike Frysinger3-11/+7
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+8
2022-11-04sim: build: remove various obsolete generation dep variablesMike Frysinger1-9/+0
2022-11-04sim: cleanup unused SIM_EXTRA_CFLAGSMike Frysinger1-2/+0
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-2/+2
2022-10-31sim: reg: constify store helperMike Frysinger1-1/+1
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-4/+2
2022-10-19sim/iq2000: silence pointer-sign warningsAndrew Burgess2-6/+6
2022-01-06sim: iq2000: migrate to standard uintXX_t typesMike Frysinger1-4/+4
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker15-15/+15
2021-12-09sim: use ## for automake commentsMike Frysinger1-19/+19
2021-11-28sim: iq2000/lm32/m32c/moxie/rx: switch to new target-newlib-syscall.hMike Frysinger1-8/+8
2021-11-16sim: callback: expose argv & environMike Frysinger1-0/+5
2021-11-16sim: keep track of program environment stringsMike Frysinger1-1/+7
2021-11-16sim: iq2000: fix some missing prototypes warningsMike Frysinger4-5/+10
2021-11-15sim: split program path out of argv vectorMike Frysinger1-5/+1
2021-11-02sim: hoist cgen mloop rules up to common buildsMike Frysinger2-12/+38
2021-11-01sim: iq2000: reduce -Wno-error scopeMike Frysinger2-5/+5
2021-10-31sim: tighten up stamp rulesMike Frysinger1-1/+2
2021-10-31sim: silence stamp touch rulesMike Frysinger1-3/+3
2021-10-31sim: standardize move-if-change rulesMike Frysinger1-2/+2
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
2021-06-30sim: cris/frv/iq2000/lm32: merge with common configure scriptMike Frysinger4-2896/+6
2021-06-30sim: unify scache settingsMike Frysinger4-34/+7
2021-06-30sim: move default model to the runtime sim stateMike Frysinger5-24/+9
2021-06-30sim: namespace sim_machsMike Frysinger3-1/+11
2021-06-29sim: model: constify sim_machs storageMike Frysinger2-1/+5
2021-06-28sim: cgen: delete unused record_trace_results functionsMike Frysinger2-8/+4
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