aboutsummaryrefslogtreecommitdiff
path: root/sim/example-synacor
AgeCommit message (Expand)AuthorFilesLines
2023-01-15sim: modules.c: fix generation after recent refactorsMike Frysinger1-0/+3
2023-01-14sim: common: move modules.c to source trackingMike Frysinger1-1/+2
2023-01-14sim: common: move libcommon.a objects to sourcesMike Frysinger1-2/+2
2023-01-11sim: build: drop subdir Makefile.in filesMike Frysinger1-19/+0
2023-01-10sim: move arch-specific file compilation of common/ files to top-levelMike Frysinger1-2/+2
2023-01-10sim: example-synacor: move arch-specific file compilation to top-levelMike Frysinger1-3/+0
2023-01-10sim: build: drop support for creating libsim.a in subdirsMike Frysinger1-3/+0
2023-01-10sim: example-synacor: move libsim.a creation to top-levelMike Frysinger2-5/+20
2023-01-01Update copyright year range in header of all files managed by GDBJoel Brobecker6-6/+6
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-23sim: example-synacor: move arch-specific settings to internal headerMike Frysinger4-14/+42
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger1-2/+0
2022-12-21sim: example-synacor: invert sim_cpu storageMike Frysinger3-37/+47
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+25
2022-01-06sim: synacor: migrate to standard uintXX_t typesMike Frysinger2-27/+27
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker4-4/+4
2021-11-16sim: callback: expose argv & environMike Frysinger1-0/+5
2021-11-16sim: keep track of program environment stringsMike Frysinger1-0/+6
2021-11-15sim: split program path out of argv vectorMike Frysinger1-4/+1
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
2021-06-22sim: drop configure scripts for simple portsMike Frysinger4-2893/+6
2021-06-21sim: unify hardware settingsMike Frysinger3-54/+5
2021-06-21sim: hw: rework configure option & device selectionMike Frysinger2-38/+30
2021-06-20sim: delete SIM_AC_COMMON macroMike Frysinger4-5/+5
2021-06-20sim: unify general maintainer settingsMike Frysinger2-124/+0
2021-06-20sim: move sim-inline to the common codeMike Frysinger3-36/+5
2021-06-19sim: unify gettext/intl probing logicMike Frysinger2-85/+0
2021-06-19sim: unify toolchain dependency logicMike Frysinger2-1109/+1
2021-06-19sim: unify toolchain probing logicMike Frysinger2-1360/+26
2021-06-19sim: unify bfd library dependency testing logicMike Frysinger3-7691/+6
2021-06-19sim: unify various library testing logicMike Frysinger2-141/+6
2021-06-18sim: unify -Werror build settingsMike Frysinger3-112/+6
2021-06-18sim: move -Werror disabling to MakefileMike Frysinger2-5/+8
2021-06-18sim: split sim-signal.h include outMike Frysinger2-0/+5
2021-06-17sim: overhaul & unify endian settings managementMike Frysinger5-59/+10
2021-06-16sim: drop obsolete AC_EXEEXT callMike Frysinger2-2/+4
2021-06-16sim: drop arch-specific config.hMike Frysinger3-280/+47
2021-06-15sim: move dv-sockser define to CPPFLAGSMike Frysinger3-8/+5
2021-06-12sim: overhaul alignment settings managementMike Frysinger5-56/+12
2021-06-12sim: unify bug & package settingsMike Frysinger3-87/+2
2021-06-12sim: unify debug/stdio/trace/profile build settingsMike Frysinger2-150/+2
2021-06-12sim: unify environment build settingsMike Frysinger3-32/+2
2021-06-12sim: unify assert build settingsMike Frysinger4-28/+6
2021-06-12sim: unify platform function & header testsMike Frysinger3-552/+6
2021-05-17sim: fully merge sim_state_base into sim_stateMike Frysinger2-2/+4
2021-05-17sim: invert sim_state storageMike Frysinger2-7/+7
2021-05-16sim: switch config.h usage to defs.hMike Frysinger3-2/+8
2021-05-16sim: riscv: move __int128 check to configureMike Frysinger3-2/+19
2021-05-14sim: create header namespaceMike Frysinger2-2/+6
2021-05-04sim: add support for build-time ar & ranlibMike Frysinger2-2/+14
generated by cgit v1.1 at 2024-11-22 12:35:59 +0000