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2022-01-06sim: erc32: migrate to standard uintXX_t typesMike Frysinger1-117/+117
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker1-1/+1
2021-10-31sim: erc32: fix a few more build warningsMike Frysinger1-5/+8
2021-10-31sim: erc32: fix signedness compatibility and redefinition warningsOrgad Shaneh1-12/+11
2021-06-14sim: erc32: fix build w/out termios.hMike Frysinger1-0/+12
2021-06-12sim: erc32: replace caddr_t with void*Mike Frysinger1-10/+10
2021-05-16sim: switch config.h usage to defs.hMike Frysinger1-1/+3
2021-04-08Do not use old-style definitions in simTom Tromey1-90/+47
2021-01-01Update copyright year range in all GDB filesJoel Brobecker1-1/+1
2020-01-01Update copyright year range in all GDB files.Joel Brobecker1-1/+1
2019-01-01Update copyright year range in all GDB files.Joel Brobecker1-1/+1
2018-01-02Update copyright year range in all GDB filesJoel Brobecker1-1/+1
2017-01-01update copyright year range in GDB filesJoel Brobecker1-1/+1
2016-01-01GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker1-1/+1
2015-05-17sim: erc32: restore attributionMike Frysinger1-1/+4
2015-05-08Switch erc32 simulator copyright headers to FSF.Joel Brobecker1-20/+14
2015-04-19sim/erc32: Switched emulated memory to host endian order.Jiri Gaisler1-141/+34
2015-03-28sim/erc32: Use memory_iread() function for instruction fetching.Jiri Gaisler1-1/+27
2015-03-28sim: erc32: strip paren from return statementsMike Frysinger1-39/+39
2015-03-16sim/erc32: use SIM_AC_OPTION_HOSTENDIAN to probe for host endianessJiri Gaisler1-1/+0
2015-02-21sim/erc32: Perform pseudo-init if binary linked to non-zero address.Jiri Gaisler1-0/+24
2014-01-07remove PARAMS from simTom Tromey1-41/+41
2012-12-19[sim] Update old contact info in GPL license noticesJoel Brobecker1-2/+1
2012-12-19Update sim copyright headers from GPLv2-or-later to GPLv3-or-later.Joel Brobecker1-1/+1
2012-08-16 * end.c: Include config.h before system header files.Nick Clifton1-0/+1
2010-05-112010-04-20 Tiemen Schut <T.Schut@sron.nl>Joel Sherrill1-3/+3
2008-11-112008-11-10 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill1-2/+3
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+1888
1999-04-16Initial creation of sourceware repositoryStan Shebs1-1495/+0
1996-07-04 * erc32.c (mec_reset mec_read mec_write memory_read memory_write),Stu Grossman1-0/+1495
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