aboutsummaryrefslogtreecommitdiff
path: root/sim/d10v
AgeCommit message (Collapse)AuthorFilesLines
2000-03-04* moved misplaced ChangeLog entryFrank Ch. Eigler1-0/+5
2000-02-22When SIM_HAVE_ENVIRONMENT: use sim_set_trace() to enable tracingAndrew Cagney3-11/+8
instead of sim_trace() to run the program; include support for ``-o'' option (operating environment); when a signal occurs, only continue execution when operating environment mode. Update d10v.
2000-02-09Report SIGBUS and halt simulation when ld/st detect a misaligned address.Andrew Cagney3-34/+80
2000-01-06import gdb-2000-01-05 snapshotJason Molenda4-27/+200
1999-12-07import gdb-1999-12-06 snapshotJason Molenda2-0/+27
1999-11-17import gdb-1999-11-16 snapshotJason Molenda4-312/+707
1999-11-02import gdb-1999-11-01 snapshotJason Molenda2-2/+7
1999-09-22import gdb-1999-09-21Jason Molenda2-7/+5
1999-09-13import gdb-1999-09-13 snapshotJason Molenda3-20/+272
1999-09-09import gdb-1999-09-08 snapshotStan Shebs3-160/+176
1999-05-11import gdb-1999-05-10Stan Shebs2-174/+308
1999-04-26import gdb-19990422 snapshotStan Shebs4-2/+46
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs11-0/+10212
1999-04-16Initial creation of sourceware repositoryStan Shebs12-9576/+0
1999-01-271999-01-26 Jason Molenda (jsm@bugshack.cygnus.com)Jason Molenda2-868/+1058
* simops.c (OP_5605): Sign extend MIN32 and MAX32 before saturation comparison. (OP_5607): Ditto. (OP_2A00): Ditto. (OP_2800): Ditto. PRs 18435 18436 18437 18439.
1998-09-30Fix PR 17387: ignore auto increment for loads where the destination registerNick Clifton1-0/+10
and the address register are the same.
1998-04-26 * configure: Regenerated to track ../common/aclocal.m4 changes.Tom Tromey5-120/+148
* config.in: Ditto. * acconfig.h: New file. * configure.in: Reverted change of Apr 24; use sinclude again.
1998-04-24 * configure: Regenerated to track ../common/aclocal.m4 changes.Tom Tromey3-39/+1786
* config.in: Ditto. * configure.in: Don't call sinclude.
1998-04-24* interp.c (struct hash_entry): OPCODE and MASK are unsigned.Andrew Cagney1-0/+57
* d10v_sim.h (remote-sim.h, sim-config.h): Include.
1998-04-01* configure.in (SIM_AC_OPTION_WARNINGS): Add.Andrew Cagney2-0/+8
configure: Re-generate.
1998-03-27Do top level sim-hw module for device tree.Andrew Cagney2-34/+136
Add to aclocal.m4, update all configure files.
1998-02-16Implement "dbt" and "rtd" instructions.Andrew Cagney2-15/+40
Import fixes to dmap_addr() from mitsu branch.
1998-02-13Implement separate user (SPU) and interrupt (SPI) stack pointers.Andrew Cagney3-0/+15
1998-02-11Don't abort() when system call is unknown.Andrew Cagney2-1/+4
1998-02-11Ensure zero-hardwired bits in DPSW remain zero.Andrew Cagney3-4/+77
1998-02-10D10v memory map changed. Update.Andrew Cagney1-136/+173
Initialize IMAP/DMAP registers to hardware reset value.
1998-01-31Add config support for the size of the target address and OF cell.Andrew Cagney1-0/+4
1998-01-26Exit status is in r0, not r2Michael Meissner1-0/+4
1998-01-25If DEBUG has 0x20 set, turn traps into batch debuggingMichael Meissner1-0/+7
1998-01-23First round of d10v ABI changesMichael Meissner2-68/+78
1998-01-22 * interp.c (UMEM_SEGMENTS): New define, set to 128.Fred Fish2-54/+134
(sim_size): Use UMEM_SEGMENTS rather than hardwired constant. (sim_close): Reset prog_bfd to NULL after closing it. Also reset prog_bfd_was_opened_p after closing prog_bfd. (sim_load): Reset prog_bfd_was_opened_p after closing prog_bfd. (sim_create_inferior): Get start address from abfd not prog_bfd. (xfer_mem): Do bounds checking on addresses and return zero length read/write on bad addresses, rather than aborting. Prepare to be able to handle xfers that cross segment boundaries, but not yet implemented. Only emit debug message when d10v_debug is set as well as DEBUG being defined.
1998-01-20* aclocal.m4: Recognize --enable-maintainer-mode.Doug Evans2-43/+90
*/configure: Regenerated.
1997-12-08Fix typo, REP_S was refering to REP_E register.Andrew Cagney2-1/+5
Add test.
1997-12-08For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: SteppingAndrew Cagney3-87/+165
through an exception may not work correctly. For GDB reads/writes to the control registers, ensure the cpu state is updated correctly.
1997-12-04Regenerate configure files.Doug Evans1-0/+4
1997-12-04Add DM (bit 4) to PSW. See 7-1 for more info.Andrew Cagney3-0/+10
Test.
1997-12-03* d10v_sim.h (SEXT56): Define.Andrew Cagney3-54/+48
* simops.c (OP_4201): For "rac", sign extend 56 bit value before it is shifted. * d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using SIGNED64 macro.
1997-12-02 * interp.c (sim_resume): Call do_2_short with LEFT_FIRST orFred Fish2-26/+36
RIGHT_FIRST, as appropriate, instead of hardcoded ints that don't match enum values. PR 13496
1997-12-02For "msbu", subtract unsigned product from ACC,Andrew Cagney2-4/+9
Test.
1997-12-02For "mulxu", store unsigned product in ACC.Andrew Cagney2-3/+7
Test.
1997-12-02For MACU add unsigned multiply to accumulator.Andrew Cagney2-4/+13
Test.
1997-12-02For sub2w, compute carry according to negated addition rules.Andrew Cagney2-4/+6
Test.
1997-12-01Rework sim/common/sim-alu.h to differentiate between direcctAndrew Cagney2-11/+40
subtraction (involves borrow) and negated addition (involves carry). Update d30v so that it uses this method. Add more tests.
1997-11-10* simops.c (OP_4201): "rachi". Sign extend bit 40 of ACC. SignAndrew Cagney1-0/+6
extend bit 44 all constants. (OP_4201): Replace GCC specific 0x..LL with SIGNED64 macro.
1997-10-25Correct name of file given in ChangeLog for change: Pass lma_p andAndrew Cagney1-1/+1
sim_write args to sim_load_file.
1997-10-24Address MSC compiler issues in d10v_sim.hAndrew Cagney1-0/+8
1997-10-22Add LMA_P and DO_WRITE arguments to sim/common/sim-load.c:sim_load_file().Andrew Cagney2-2/+29
Update all simulators. Clarify behavour of sim_load in remote-sim.h
1997-10-13 * simops.c (OP_6A01): Change OP_POSTDEC to OP_POSTINC and moveFred Fish2-8/+15
exception generation code to OP_6E01. (OP_6E01): Change OP_POSTINC to OP_POSTDEC and insert exception generation code. PR 13550
1997-10-11 * simops.c (OP_6401): postdecrement on r15 is OK, remove exception.Fred Fish1-15/+3
(OP_6601): Ditto. PR 13498
1997-10-11 * simops.c (OP_6401): postdecrement on r15 is OK, remove exception.Fred Fish1-0/+9
(OP_6601): Ditto.
generated by cgit v1.1 at 2024-11-25 14:10:26 +0000