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path: root/sim/d10v/interp.c
AgeCommit message (Expand)AuthorFilesLines
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-23sim: d10v: move arch-specific settings to internal headerMike Frysinger1-0/+2
2022-12-22sim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]Mike Frysinger1-6/+6
2022-12-20sim: move register headers into sim/ namespace [PR sim/29869]Mike Frysinger1-1/+1
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-4/+4
2022-10-31sim: reg: constify store helperMike Frysinger1-2/+2
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-2/+2
2022-08-06Don't use BFD_VMA_FMT in gdb and simAlan Modra1-2/+2
2022-01-06sim: d10v: migrate to standard uintXX_t typesMike Frysinger1-33/+33
2021-11-28sim: d10v: switch to new target-newlib-syscallMike Frysinger1-0/+3
2021-11-15sim: split program path out of argv vectorMike Frysinger1-4/+1
2021-11-01sim: d10v: clean up pointer castsMike Frysinger1-6/+6
2021-06-18sim: split sim-signal.h include outMike Frysinger1-0/+1
2021-06-12sim: overhaul alignment settings managementMike Frysinger1-0/+3
2021-05-21sim/d10v: Use offsetof in a static assertion about structure layout.John Baldwin1-2/+2
2021-05-16sim: switch config.h usage to defs.hMike Frysinger1-1/+3
2021-05-14sim: create header namespaceMike Frysinger1-2/+2
2021-05-12Fix build failure in d10v simLuis Machado1-2/+7
2021-05-04sim: clean up bfd_vma printingMike Frysinger1-1/+2
2021-04-18sim: d10v: fix build warningsMike Frysinger1-3/+5
2021-04-12sim: cgen: move cgen_cpu_max_extra_bytes logic into the common codeMike Frysinger1-1/+1
2021-01-11sim: clean up C11 header includesMike Frysinger1-9/+0
2021-01-09sim: cr16/d10v: move storage out of headerMike Frysinger1-0/+2
2016-01-06sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger1-2/+4
2016-01-03sim: parse_args: display getopt error ourselvesMike Frysinger1-3/+1
2015-12-30sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to...Mike Frysinger1-6/+11
2015-11-15sim: cr16/d10v: drop redundant call to sim_create_inferiorMike Frysinger1-1/+0
2015-11-15sim: d10v: drop global callback stateMike Frysinger1-63/+59
2015-11-15sim: d10v: convert to common sim engine logicMike Frysinger1-118/+59
2015-11-15sim: d10v: push down sd/cpu varsMike Frysinger1-82/+101
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger1-7/+0
2015-11-10sim: cr16/d10v: localize translation funcsMike Frysinger1-3/+3
2015-04-17sim: arm/cr16/d10v/h8300/microblaze/sh: fill out sim-cpu pc fetch/store helpersMike Frysinger1-0/+22
2015-04-02sim: d10v: fix signal updatesMike Frysinger1-8/+5
2015-04-01sim: run: punt!Mike Frysinger1-2/+0
2015-03-30sim: d10v: convert to nrunMike Frysinger1-115/+68
2015-03-30sim: d10v: delete NEED_UI_LOOP_HOOK handlingMike Frysinger1-19/+0
2015-03-30sim: d10v: clean up misc warningsMike Frysinger1-81/+27
2015-03-30sim: d10v: use common configure optionsMike Frysinger1-0/+8
2014-03-10sim: constify arg to sim_do_commandMike Frysinger1-1/+1
2014-03-05sim: constify prog_nameMike Frysinger1-1/+1
2014-01-07remove PARAMS from simTom Tromey1-10/+10
2012-06-19include "config.h" instead of BFD's sysdep.h in d10v/interp.cJoel Brobecker1-1/+13
2012-05-24gdb/Pedro Alves1-2/+2
2010-04-14sim: constify sim_write source buffer (part 2)Mike Frysinger1-1/+1
2006-04-18* interp.c (sim_stop_reason): Fix typo.Nick Clifton1-1/+1
2005-11-28 * remote-sim.c (gdbsim_wait): Pass target signal numbers toMark Mitchell1-6/+3
2004-06-29Index: mn10200/ChangeLogAndrew Cagney1-3/+3
2003-06-222003-06-22 Andrew Cagney <cagney@redhat.com>Andrew Cagney1-36/+26
2003-05-07Index: gdb/ChangeLogAndrew Cagney1-18/+24
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