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AgeCommit message (Expand)AuthorFilesLines
2023-01-05sim: Move getopt checking inside SIM_AC_PLATFORMTsukasa OI1-10/+0
2023-01-02sim: build: add var for tracking sim enable directlyMike Frysinger1-1/+3
2023-01-02sim: build: use Automake include varsMike Frysinger1-5/+0
2022-12-25sim: smp: make option available againMike Frysinger1-0/+1
2022-12-24sim: mips: clean up a bit after mips/configure removalMike Frysinger1-1/+1
2022-12-24sim: mips: move igen settings to top-level configureMike Frysinger1-1/+1
2022-12-21sim: mips: move subtarget defines to top-level configureMike Frysinger1-0/+1
2022-11-07sim: v850: drop subdir configure logicMike Frysinger1-1/+1
2022-11-07sim: mn10300: drop subdir configure logicMike Frysinger1-1/+1
2022-11-07sim: or1k: drop subdir configure logicMike Frysinger1-1/+1
2022-11-07sim: bpf: drop subdir configure logicMike Frysinger1-1/+1
2022-11-07sim: riscv: drop subdir configure logicMike Frysinger1-1/+2
2022-11-07sim: .gdbinit: generate for all arch subdirsMike Frysinger1-1/+1
2022-11-07sim: build: add a proper var for enabled archesMike Frysinger1-0/+6
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+1
2022-11-03sim: merge gnulib logic into the top-levelMike Frysinger1-0/+5
2022-10-11sim: Check known getopt definition existenceTsukasa OI1-0/+10
2022-03-28sim: add arch/.gdbinit stub scriptsMike Frysinger1-0/+1
2022-02-21sim: gdbinit: hoist setup to common codeMike Frysinger1-1/+1
2021-11-28sim: testsuite: setup per-port toolchain settings for multitarget buildMike Frysinger1-0/+2
2021-11-18sim: avoid installing headers when there is no simMike Frysinger1-0/+1
2021-10-31sim: add arch-specific conditional logicMike Frysinger1-0/+3
2021-09-08sim: update configure target listMike Frysinger1-4/+7
2021-07-01sim: unify reserved instruction bits settingsMike Frysinger1-1/+1
2021-07-01sim: m32r: merge with common configure scriptMike Frysinger1-1/+1
2021-06-30sim: cris/frv/iq2000/lm32: merge with common configure scriptMike Frysinger1-4/+5
2021-06-30sim: unify scache settingsMike Frysinger1-1/+1
2021-06-30sim: bfin: merge with common configure scriptMike Frysinger1-1/+1
2021-06-30sim: move default model to the runtime sim stateMike Frysinger1-1/+0
2021-06-27sim: erc32: merge with common configure scriptMike Frysinger1-1/+1
2021-06-23sim: switch common srcdir to abs_srcdirMike Frysinger1-1/+1
2021-06-22sim: rx: merge with common configure scriptMike Frysinger1-1/+4
2021-06-22sim: drop configure scripts for simple portsMike Frysinger1-19/+65
2021-06-21sim: unify hardware settingsMike Frysinger1-0/+1
2021-06-20sim: unify cgen maintainer settingsMike Frysinger1-0/+1
2021-06-20sim: move sim-inline to the common codeMike Frysinger1-0/+1
2021-06-19sim: unify toolchain dependency logicMike Frysinger1-3/+10
2021-06-18sim: unify -Werror build settingsMike Frysinger1-0/+1
2021-06-18sim: create a makefile fragment to pass common settings downMike Frysinger1-1/+1
2021-06-17sim: overhaul & unify endian settings managementMike Frysinger1-0/+1
2021-06-14sim: enable silent rules in common buildsMike Frysinger1-0/+1
2021-06-12sim: overhaul alignment settings managementMike Frysinger1-0/+1
2021-06-12sim: unify bug & package settingsMike Frysinger1-0/+7
2021-06-12sim: unify debug/stdio/trace/profile build settingsMike Frysinger1-0/+6
2021-06-12sim: unify environment build settingsMike Frysinger1-0/+1
2021-06-12sim: unify assert build settingsMike Frysinger1-0/+2
2021-06-12sim: unify platform function & header testsMike Frysinger1-0/+3
2021-04-03sim: example-synacor: a simple implementation for referenceMike Frysinger1-0/+8
2021-04-03sim: add preliminary support for --enable-targetsMike Frysinger1-98/+60
2021-04-02sim: igen: merge build into top levelMike Frysinger1-3/+1
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