aboutsummaryrefslogtreecommitdiff
path: root/sim/common/sim-core.c
AgeCommit message (Expand)AuthorFilesLines
2003-12-19Add support for m32r-linux target, including a RELA ABI and PIC.Nick Clifton1-0/+19
2002-11-232002-11-22 Andrew Cagney <ac131313@redhat.com>Andrew Cagney1-19/+22
2001-03-16* tweakFrank Ch. Eigler1-3/+3
1999-04-26import gdb-19990422 snapshotStan Shebs1-9/+6
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+839
1999-04-16Initial creation of sourceware repositoryStan Shebs1-820/+0
1998-06-11 * sim-core.h (SIM_CORE_SIGNAL_FN): New typedef.Doug Evans1-130/+155
1998-03-04 * sim-core.c (sim_core_attach): Use xmalloc instead of zalloc.Doug Evans1-6/+3
1998-03-03Good grief. Detailed function descriptions should accompany their definition.Doug Evans1-11/+1
1998-03-03(sim_core_attach): Add a comment describing its function.Doug Evans1-1/+13
1998-03-02 * sim-core.c (sim_core_attach): Revise last patch.Doug Evans1-1/+4
1998-03-02 * sim-core.c (sim_core_attach): Use xmalloc instead of zalloc.Doug Evans1-2/+3
1998-02-25 (profile_print_core): Simplify by calling sim_core_map_to_str.Doug Evans1-1/+1
1998-02-20Backout of revision 1.35. Abort may be valid operation.Andrew Cagney1-3/+14
1997-11-19 * sim-core.c (sim_core_signal): Use sim_stopped instead ofDoug Evans1-2/+2
1997-11-19 * sim-signal.c, sim-signal.h: New files.Doug Evans1-11/+2
1997-11-18 * sim-core.c (sim_core_signal): Use CIA_ADDR to fetch value.Doug Evans1-3/+1
1997-11-14(sim_core_signal): Add missing "\n" in message.Doug Evans1-4/+7
1997-11-05Rewrite the MIPS simulator's memory model so that it uses the genericAndrew Cagney1-9/+20
1997-10-31Make memory regions layered (just like existing device regions) soAndrew Cagney1-68/+61
1997-10-28Implement sim_core_{read,write}_word using sim_core_{read,write}_<N>.Andrew Cagney1-4/+0
1997-10-27Add 128 bit transfers to sim core.Andrew Cagney1-1/+5
1997-10-14Handle core regions which start at a poorly aligned address.Andrew Cagney1-25/+37
1997-09-10 * sim-core.h (sim_cpu_core): [WITH_XOR_ENDIAN + 1], to avoidFelix Lee1-1/+1
1997-09-05Redo watchpoint code so that it target can specify interrupt names.Andrew Cagney1-3/+7
1997-09-05Define SIGNED64 and UNSIGNED64 macros - handle MSC/GCC LL issue.Andrew Cagney1-1/+1
1997-09-04o Add modulo argument to sim_core_attachAndrew Cagney1-125/+224
1997-09-03Stanify error reporting memory overlaps.Andrew Cagney1-8/+23
1997-08-30Passify GCC. Convert 0x0LL to something more portable in the FP code.Andrew Cagney1-55/+199
1997-05-23Preliminary suport for xor-endian suport in core module.Andrew Cagney1-19/+58
1997-05-21Watchpoint interface.Andrew Cagney1-15/+49
1997-05-12c80 simulator fixes.Andrew Cagney1-1/+1
1997-05-05Start of implementation of a distributed (between processors)Andrew Cagney1-31/+52
1997-05-02Update devo version of m32r sim to build with recent sim/common changes.Andrew Cagney1-8/+24
1997-05-01 * Makefile.in (sim-options_h): Define.David Edelsohn1-57/+83
1997-03-14Add a number of per-simulator options: hostendian, endian, inline, warnings.Andrew Cagney1-0/+375
generated by cgit v1.1 at 2024-07-13 14:45:55 +0000