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2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-8164/+0
2021-07-01sim: unify reserved instruction bits settingsMike Frysinger1-0/+4
2021-07-01cgen: split GUILE setting outMike Frysinger1-0/+5
2021-06-30sim: unify scache settingsMike Frysinger1-0/+6
2021-06-30sim: move scache init to dynamic modules.cMike Frysinger1-0/+7
2021-06-30sim: move profile init to dynamic modules.cMike Frysinger1-0/+7
2021-06-30sim: move trace init to dynamic modules.cMike Frysinger1-0/+7
2021-06-30sim: move engine init to dynamic modules.cMike Frysinger1-0/+7
2021-06-30sim: delete unused model settingsMike Frysinger1-0/+6
2021-06-30sim: move default model to the runtime sim stateMike Frysinger1-0/+11
2021-06-30sim: namespace sim_machsMike Frysinger1-0/+24
2021-06-29sim: fix arch Makefile regen when unifiedMike Frysinger1-0/+5
2021-06-29sim: callback: add check for HAVE_KILLMike Frysinger1-0/+4
2021-06-29sim: model: constify sim_machs storageMike Frysinger1-0/+9
2021-06-29sim: io: add printf attributes to vprintf funcs tooMike Frysinger1-0/+5
2021-06-29sim: callback: add printf attributesMike Frysinger1-0/+4
2021-06-29sim: callback: drop unused printf helpersMike Frysinger1-0/+6
2021-06-29sim: cgen: require long long supportMike Frysinger1-0/+6
2021-06-27sim: cgen: suppress trace non-literal printf warningMike Frysinger1-0/+6
2021-06-27sim: cgen: add asserts to fix unused engine warningsMike Frysinger1-0/+4
2021-06-27sim: cgen: add printf attributes in a few more callsMike Frysinger1-0/+5
2021-06-27sim: cgen: constify trace stringsMike Frysinger1-0/+9
2021-06-27sim: cgen: always leverage the mem prototypesMike Frysinger1-0/+13
2021-06-27sim: cgen: always leverage the ops prototypesMike Frysinger1-0/+4
2021-06-27sim: cgen: sync prototypes with implementationMike Frysinger1-0/+9
2021-06-23sim: syscall: handle killing the sim itselfMike Frysinger1-0/+4
2021-06-23sim: callback: add a kill interfaceMike Frysinger1-0/+6
2021-06-23sim: switch common srcdir to abs_srcdirMike Frysinger1-0/+4
2021-06-22sim: callback: add missing cb_target_to_host_signalMike Frysinger1-0/+4
2021-06-22sim: callback: generate signal mapMike Frysinger1-0/+9
2021-06-22sim: callback: add a getpid interfaceMike Frysinger1-0/+6
2021-06-22sim: drop configure scripts for simple portsMike Frysinger1-0/+9
2021-06-21sim: unify hardware settingsMike Frysinger1-0/+4
2021-06-21sim: hw: rework configure option & device selectionMike Frysinger1-0/+7
2021-06-20sim: unify cgen maintainer settingsMike Frysinger1-0/+4
2021-06-20sim: move sim-inline to the common codeMike Frysinger1-0/+4
2021-06-19sim: move UNUSED before TYPE in SIM_ENDIAN_INLINE's definitionSimon Marchi1-0/+4
2021-06-19sim: drop old BUILT_SRC_FROM_COMMON refMike Frysinger1-0/+4
2021-06-19sim: unify gettext/intl probing logicMike Frysinger1-0/+5
2021-06-19sim: unify toolchain dependency logicMike Frysinger1-0/+4
2021-06-19sim: unify toolchain probing logicMike Frysinger1-0/+4
2021-06-19sim: unify bfd library dependency testing logicMike Frysinger1-0/+6
2021-06-19sim: unify various library testing logicMike Frysinger1-0/+4
2021-06-18sim: unify -Werror build settingsMike Frysinger1-0/+4
2021-06-18sim: create a makefile fragment to pass common settings downMike Frysinger1-0/+4
2021-06-18sim: split sim-signal.h include outMike Frysinger1-0/+7
2021-06-18sim: drop core libiberty.h includeMike Frysinger1-0/+4
2021-06-17sim: overhaul & unify endian settings managementMike Frysinger1-0/+8
2021-06-17sim: split sim/callback.h include outMike Frysinger1-0/+9
2021-06-16sim: drop arch-specific config.hMike Frysinger1-0/+9
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