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path: root/sim/bfin/interp.c
AgeCommit message (Expand)AuthorFilesLines
2023-01-01sim: replace -I$srcroot/bfd include with -I$srcrootMike Frysinger1-1/+1
2023-01-01Update copyright year range in header of all files managed by GDBJoel Brobecker1-1/+1
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-23sim: bfin: move arch-specific settings to internal headerMike Frysinger1-0/+3
2022-12-22sim: use bfd_vma when reading start addr from bfd infoMike Frysinger1-1/+1
2022-12-21sim: bfin: invert sim_cpu storageMike Frysinger1-3/+2
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-14/+14
2022-05-13sim: remove use of PTRAlan Modra1-2/+2
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker1-1/+1
2021-11-16sim: syscall: hoist argc/argn/argnlen to common codeMike Frysinger1-33/+0
2021-11-16sim: callback: expose argv & environMike Frysinger1-0/+4
2021-11-16sim: keep track of program environment stringsMike Frysinger1-0/+6
2021-11-15sim: split program path out of argv vectorMike Frysinger1-4/+1
2021-08-17sim: nltvals: localize TARGET_<ERRNO> definesMike Frysinger1-12/+10
2021-06-30sim: move default model to the runtime sim stateMike Frysinger1-0/+1
2021-06-30sim: namespace sim_machsMike Frysinger1-0/+1
2021-06-24sim: callback: extend syscall interface to handle 7 argsMike Frysinger1-4/+4
2021-06-17sim: overhaul & unify endian settings managementMike Frysinger1-0/+1
2021-06-12sim: start unifying portability shimsMike Frysinger1-19/+1
2021-06-12sim: overhaul alignment settings managementMike Frysinger1-0/+3
2021-05-17sim: bfin: invert sim_state storageMike Frysinger1-1/+2
2021-05-16sim: switch config.h usage to defs.hMike Frysinger1-1/+2
2021-05-14sim: create header namespaceMike Frysinger1-1/+1
2021-05-03sim: add ATTRIBUTE_PRINTF / ATTRIBUTE_NULL_PRINTF where necessarySimon Marchi1-1/+1
2021-05-01sim: bfin: move option inits to respective modulesMike Frysinger1-11/+0
2021-04-18sim: syscall: add getpid supportMike Frysinger1-4/+0
2021-04-12sim: cgen: move cgen_cpu_max_extra_bytes logic into the common codeMike Frysinger1-1/+1
2021-02-06sim: watchpoints: use common sim_pc_getMike Frysinger1-6/+0
2021-01-30sim: watchpoints: change sizeof_pc to sizeof(sim_cia)Mike Frysinger1-1/+0
2021-01-02sim: common: add align_{up,down} to match gdbMike Frysinger1-3/+4
2021-01-01Update copyright year range in all GDB filesJoel Brobecker1-1/+1
2020-01-01Update copyright year range in all GDB files.Joel Brobecker1-1/+1
2019-01-01Update copyright year range in all GDB files.Joel Brobecker1-1/+1
2018-01-02Update copyright year range in all GDB filesJoel Brobecker1-1/+1
2017-01-01update copyright year range in GDB filesJoel Brobecker1-1/+1
2016-01-06sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger1-8/+8
2016-01-05sim: bfin: add support disasm tracingMike Frysinger1-0/+2
2016-01-04sim: unify min/max macrosMike Frysinger1-2/+2
2016-01-03sim: parse_args: display getopt error ourselvesMike Frysinger1-3/+1
2016-01-03sim: use libiberty countargv in more placesMike Frysinger1-19/+5
2016-01-01GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker1-1/+1
2015-12-26sim: standardize sim_create_inferior handling of argv a bit moreMike Frysinger1-4/+5
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger1-6/+0
2015-06-24sim: trace: add a basic cpu register classMike Frysinger1-16/+0
2015-06-17sim: syscall: unify memory helpersMike Frysinger1-28/+3
2015-06-12sim: bfin: expand CB_SYS_xxx commentMike Frysinger1-1/+3
2015-06-12sim: trace: add common macros for logging infoMike Frysinger1-2/+2
2015-01-01Update year range in copyright notice of all files owned by the GDB project.Joel Brobecker1-1/+1
2014-01-01Update Copyright year range in all files maintained by GDB.Joel Brobecker1-1/+1
2013-01-01Update years in copyright notice for the GDB files.Joel Brobecker1-1/+1
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