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path: root/sim/avr/interp.c
AgeCommit message (Expand)AuthorFilesLines
2023-01-01Update copyright year range in header of all files managed by GDBJoel Brobecker1-1/+1
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-23sim: avr: move arch-specific settings to internal headerMike Frysinger1-0/+1
2022-12-22sim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]Mike Frysinger1-4/+4
2022-12-22sim: use bfd_vma when reading start addr from bfd infoMike Frysinger1-1/+1
2022-12-21sim: avr: invert sim_cpu storageMike Frysinger1-96/+103
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-2/+6
2022-10-31sim: reg: constify store helperMike Frysinger1-1/+1
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-6/+8
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker1-1/+1
2021-11-15sim: split program path out of argv vectorMike Frysinger1-4/+1
2021-06-18sim: split sim-signal.h include outMike Frysinger1-0/+1
2021-06-17sim: overhaul & unify endian settings managementMike Frysinger1-0/+1
2021-06-12sim: overhaul alignment settings managementMike Frysinger1-0/+3
2021-05-17sim: avr: invert sim_state storageMike Frysinger1-6/+7
2021-05-16sim: switch config.h usage to defs.hMike Frysinger1-1/+2
2021-05-14sim: create header namespaceMike Frysinger1-1/+1
2021-04-12sim: cgen: move cgen_cpu_max_extra_bytes logic into the common codeMike Frysinger1-1/+1
2021-02-06sim: watchpoints: use common sim_pc_getMike Frysinger1-6/+0
2021-01-30sim: watchpoints: change sizeof_pc to sizeof(sim_cia)Mike Frysinger1-1/+0
2021-01-11sim: clean up C11 header includesMike Frysinger1-2/+1
2021-01-01Update copyright year range in all GDB filesJoel Brobecker1-1/+1
2020-01-01Update copyright year range in all GDB files.Joel Brobecker1-1/+1
2019-01-01Update copyright year range in all GDB files.Joel Brobecker1-1/+1
2018-01-02Update copyright year range in all GDB filesJoel Brobecker1-1/+1
2017-01-01update copyright year range in GDB filesJoel Brobecker1-1/+1
2016-07-19 Update PC when simulate break instruction.Denis Chertykov1-2/+1
2016-01-06sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger1-2/+4
2016-01-03sim: parse_args: display getopt error ourselvesMike Frysinger1-3/+1
2016-01-01GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker1-1/+1
2015-12-15Fix invalid left shift of negative valueDominik Vogt1-1/+1
2015-11-22sim: avr: move global state to sim/cpu stateMike Frysinger1-131/+132
2015-11-22sim: avr: switch to common sim-regMike Frysinger1-4/+6
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger1-6/+0
2015-04-16sim: avr/mcore/moxie: fill out sim-cpu pc fetch/store helpersMike Frysinger1-0/+22
2015-03-28sim: avr: convert to nrun.oMike Frysinger1-831/+734
2015-02-19sim: drop unused sim_kill functionMike Frysinger1-6/+0
2015-01-01Update year range in copyright notice of all files owned by the GDB project.Joel Brobecker1-1/+1
2014-03-10sim: constify arg to sim_do_commandMike Frysinger1-1/+1
2014-03-05sim: constify prog_nameMike Frysinger1-1/+1
2014-01-01Update Copyright year range in all files maintained by GDB.Joel Brobecker1-1/+1
2013-03-15gdb:Steve Ellcey1-1/+1
2013-01-01Update years in copyright notice for the GDB files.Joel Brobecker1-1/+1
2012-05-24gdb/Pedro Alves1-3/+3
2012-01-04Copyright year update in most files of the GDB Project.Joel Brobecker1-1/+1
2011-04-16sim: add sim_complete_command stubs for non-common-using portsMike Frysinger1-0/+6
2011-01-01run copyright.sh for 2011.Joel Brobecker1-1/+1
2010-04-14sim: constify sim_write source buffer (part 2)Mike Frysinger1-1/+1
2010-01-01Update copyright notices to add year 2010.Joel Brobecker1-1/+1
2009-11-122009-11-12 Tristan Gingold <gingold@adacore.com>Tristan Gingold1-16/+20
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