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2003-01-102003-01-10 Ben Elliston <bje@redhat.com>Ben Elliston2-0/+5
* README.Cygnus: Rename from this .. * README: .. to this.
2003-01-10* remove duplicated entry from 2002-05-17 on 2002-05-20.Ben Elliston1-23/+1
* s/SWI_TARGET_SWITCHES/SIM_TARGET_SWITCHES/.
2002-09-27Add support for -m option. Fix PR gdb/433.Andrew Cagney2-2/+25
2002-08-16oops - fix typo in previous deltaNick Clifton1-2/+2
2002-08-15Catch and ignore SWIs of -1, they can be caused by an interrupted systemNick Clifton2-0/+19
call being resumed by GDB.
2002-07-05Add checks to catch invaliud XScale MIA, MIAPH and MIAxy instructions.Nick Clifton2-68/+79
2002-06-21Set correct value for ADP_Stopped_RunTimeErrorNick Clifton2-40/+41
2002-06-16Import current --enable-gdb-build-warnings.Andrew Cagney2-0/+6
2002-06-12Add the file include/gdb/sim-arm.h defining an enum that specifies theAndrew Cagney3-12/+91
register numbering used by the GDB<->SIM interface.
2002-06-09Move include/callback.h and include/remote-sim.h to include/gdb/.Andrew Cagney3-3/+8
Update accordingly.
2002-05-29Set the FSR and FAR registers if a Data Abort is detected.Nick Clifton2-1/+13
2002-05-27Only perform access checks if 'check' is set.Nick Clifton7-18/+25
Report unknown machine numbers. Formatting tidy ups.
2002-05-27Thumb BL instruction: Do not set LR to pc + 2, it has already been advanced.Nick Clifton2-4/+11
2002-05-23When decoding a BLX(1) instruction do not add in the second bit of the baseNick Clifton2-5/+8
address - this has already been accounted for.
2002-05-21Simulate XScale BCUMOD registerNick Clifton2-3/+15
2002-05-20Add support for target specific command line switches to old-style simualtors.Nick Clifton5-250/+464
Make use of this support in the ARM simulator to add a --swi-support= switch to select whcih SWI protocols to emulate.
2002-05-09Uses sim callback interface for system calls in RedBoot SWI support.Nick Clifton1-8/+13
2002-05-09Support the RedBoot SWI in ARM mode and some of its system calls.Nick Clifton2-30/+109
2002-03-18Increase default memory size to 8MB.Anthony Green2-1/+5
2002-02-21 * armos.c (SWIWrite0): Use generic host_callback mechanismKeith Seitz2-31/+50
for supported OS functions "open", "close", "write", etc. (SWIopen): Likewise. (SWIread): Likewise. (SWIwrite): Likewise. (SWIflen): Likewise. (ARMul_OSHandleSWI): Likewise.
2002-02-05Modify previous patch so that it is only triggered for COFF format executables.Nick Clifton2-11/+20
2002-02-04If a v5 architecture is detected, assume it might be an XScale binary, sinceNick Clifton2-0/+15
there is no way to distinguish between the two in the COFF file format.
2002-01-10Fix parameters passed to CPRead[13] and CPRead[14].Nick Clifton4-423/+478
2002-01-09General format tidy upsNick Clifton2-45/+51
2002-01-09Fix bug detected by GDB testsuite - when fetching registers more than 4Nick Clifton2-5/+19
bytes wide return 0 for the other bytes.
2001-11-162001-11-16 Ben Harris <bjh21@netbsd.org>Ben Harris2-2/+8
* Makefile.in (armemu32.o): Replace $< with autoconf recommended $(srcdir)/.... (armemu26.o): Ditto.
2001-10-18Add support for XScale's coprocessor access check register.Nick Clifton5-988/+944
Fix formatting.
2001-05-11Fix handling of XScale LDRD and STRD instructions with post indexed ↵Nick Clifton2-6/+11
addressing modes.
2001-05-08Check Mode not Bank in order to determine rocesor mode.Nick Clifton2-1/+7
2001-04-18* XScale coprocessor support.Matthew Green6-22/+284
2001-04-18 matthew green <mrg@redhat.com> * armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes. (read_cp15_reg): Make non-static. (XScale_cp15_LDC): Update for write_cp15_reg() change. (XScale_cp15_MCR): Likewise. (XScale_cp15_write_reg): Likewise. (XScale_check_memacc): New function. Check for breakpoints being activated by memory accesses. Does not support the Branch Target Buffer. (XScale_set_fsr_far): New function. Set FSR and FAR for XScale. (XScale_debug_moe): New function. Set the debug Method Of Entry, if configured. (write_cp14_reg): Reset count counter if requested. * armdefs.h (struct ARMul_State): New members `LastTime' and `CP14R0_CCD' used for the timer/counters. (ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS, ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD, ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2, ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2, ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT, ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X, ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT, ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New defines for XScale registers. (XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype. (ARMul_Emulate32, ARMul_Emulate26): Clean up function definition. (ARMul_Emulate32): Handle the clock counter and hardware instruction breakpoints. Call XScale_set_fsr_far() for software breakpoints and software interrupts. (LoadMult): Call XScale_set_fsr_far() for data aborts. (LoadSMult): Likewise. (StoreMult): Likewise. (StoreSMult): Likewise. * armemu.h (write_cp15_reg): Update prototype. * arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime. (ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13 register 0. * armvirt.c (GetWord): Call XScale_check_memacc(). (PutWord): Likewise.
2001-03-20Do not enable alignment checking when loading unaligned thumb instructions.Nick Clifton2-2/+7
2001-03-06Fix BLX(1) for ThumbNick Clifton2-5/+24
2001-02-28Add support for disabling alignment checks when performing GDB interfaceNick Clifton8-44/+95
calls or SWI emulaiton routines. (Alignment checking code has not yet been contributed).
2001-02-16Remove Prefetch abort for breakpoints. Instead set the state to RESUME.Nick Clifton2-12/+7
2001-02-15Add code to preserve processor mode when a prefetchNick Clifton2-0/+14
abort is signalled after processing a breakpoint.
2001-02-14Reset processor into ARM mode for any machine type except the early ARMs.Nick Clifton2-12/+20
2001-02-14remove spurious whitespaceNick Clifton1-6/+6
2001-02-14Prevent Aborts from happening whilst emulating a SWINick Clifton2-62/+83
2001-02-12Fix definition of NEGBRANCHNick Clifton2-1/+6
2001-02-01Add parentheses ready for future conbtributionNick Clifton1-39/+63
2001-02-01Update base address register after restoring register bank.Nick Clifton2-26/+64
2001-02-01Detect installation of SWI vector by running program as well as loading program.Nick Clifton5-7/+18
2000-12-19Fix test for StoreDouble Instruction.Nick Clifton2-12/+17
2000-12-11Add 0x91 as an FPE SWI.Nick Clifton2-0/+5
2000-12-08oops - remove redundant prototype introduced in previous deltaNick Clifton1-2/+0
2000-12-08Add emulation of double word load and store instructions.Nick Clifton2-3/+348
2000-12-03Suppress support of DEMON swi's in XScale mode.Nick Clifton2-71/+109
2000-11-30Add support for ARM's v5TE architecture and Intel's XScale extenstionsNick Clifton10-250/+1763
2000-09-15Replace StrongARM property with v4 and v5 properties.Nick Clifton6-90/+119
2000-08-15Compute write back value for post increment loads beforeNick Clifton2-34/+47
performing the load in case the offset register is overwritten.
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