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2021-05-16sim: switch config.h usage to defs.hMike Frysinger1-0/+3
The defs.h header will take care of including the various config.h headers. For now, it's just config.h, but we'll add more when we integrate gnulib in. This header should be used instead of config.h, and should be the first include in every .c file. We won't rely on the old behavior where we expected files to include the port's sim-main.h which then includes the common sim-basics.h which then includes config.h. We have a ton of code that includes things before sim-main.h, and it sometimes needs to be that way. Creating a dedicated header avoids the ordering mess and implicit inclusion that shows up otherwise.
2021-04-26Fix a bug in the ARM emulator which would not allow 4 byte alignment for ↵Nick Clifton1-1/+4
double word stores. PR 22790 * armemu.c (Handle_Store_Double): Allow 4 byte alignment when running in v6 mode.
2020-12-15Add support for the SDIV and UDIV instructions to the ARM simulator.Jens Bauer1-1/+62
* armemu.c (handle_v6_insn): Add support for SDIV and UDIV. * thumbemu.c (handle_T2_insn): Likewise.
2019-12-06[ARM, sim] Fix build error and warningsLuis Machado1-4/+0
Newer GCC's have switched to -fno-common by default, and this breaks the build for the ARM sim, like this: binutils-gdb.git~gdb-8.3-release/sim/arm/maverick.c:65: multiple definition of `DSPsc'; libsim.a(wrapper.o):binutils-gdb.git~gdb-8.3-release/sim/arm/wrapper.c:134: first defined here binutils-gdb.git~gdb-8.3-release/sim/arm/maverick.c:64: multiple definition of `DSPacc'; libsim.a(wrapper.o):binutils-gdb.git~gdb-8.3-release/sim/arm/wrapper.c:133: first defined here binutils-gdb.git~gdb-8.3-release/sim/arm/maverick.c:63: multiple definition of `DSPregs'; libsim.a(wrapper.o):binutils-gdb.git~gdb-8.3-release/sim/arm/wrapper.c:132: first defined here I also noticed a few warnings due to mismatching types, as follows: ../../../../repos/binutils-gdb/sim/arm/wrapper.c: In function ‘sim_create_inferior’: ../../../../repos/binutils-gdb/sim/arm/wrapper.c:335:16: warning: assignment discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] for (arg = argv; *arg != NULL; arg++) ^ ../../../../repos/binutils-gdb/sim/arm/wrapper.c:342:8: warning: assignment discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] arg = argv; ^ ../../../../repos/binutils-gdb/sim/arm/wrapper.c:345:13: warning: assignment discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] for (arg = argv; *arg != NULL; arg++) ^ The following patch fixes both of the above. sim/arm/ChangeLog: 2019-12-06 Luis Machado <luis.machado@linaro.org> * armemu.c (isize): Move this declaration ... * arminit.c (isize): ... here. * maverick.h: New file. * wrapper.c: Include "maverick.h". (<struct maverick_regs>, <union maverick_acc_regs>): Remove and update comment. (sim_create_inferior): Cast variables to proper type. * maverick.c: Include "maverick.h". (<struct maverick_regs>, <union maverick_acc_regs>): Move declarations to maverick.h and update comment. (DSPsc, DSPacc, DSPregs): Adjust comment. Change-Id: I21db699d3b61b2de8c44053e47be4387285af28f
2016-07-14Small improvements to the ARM simulator to cope with illegal binaries.Nick Clifton1-3/+3
* armemu.c (Multiply64): Only issue error messages about invalid arguments if debugging is enabled. * armos.c (ARMul_OSHandleSWI): Ignore invalid flags.
2015-12-25sim: arm: delete unused codeMike Frysinger1-1/+0
These vestiges of the 20 year old emulator are just getting in the way. Punt all the dead code we either don't compile or don't use.
2015-12-15Fix invalid left shift of negative valueDominik Vogt1-20/+20
Fix occurrences of left-shifting negative constants in C code. sim/arm/ChangeLog: * thumbemu.c (handle_T2_insn): Fix left shift of negative value. * armemu.c (handle_v6_insn): Likewise. sim/avr/ChangeLog: * interp.c (sign_ext): Fix left shift of negative value. sim/mips/ChangeLog: * micromips.igen (process_isa_mode): Fix left shift of negative value. sim/msp430/ChangeLog: * msp430-sim.c (get_op, put_op): Fix left shift of negative value. sim/v850/ChangeLog: * simops.c (v850_bins): Fix left shift of negative value.
2015-06-28Add support for ARM v6 instructions.Nick Clifton1-68/+920
* Makefile.in (SIM_EXTRA_CFLAGS): Add -lm. * armdefs.h (ARMdval, ARMfval): New types. (ARM_VFP_reg): New union. (struct ARMul_State): Add VFP_Reg and FPSCR fields. (VFP_fval, VFP_uword, VFP_sword, VFP_dval, VFP_dword): Accessor macros for the new VFP_Reg field. * armemu.c (handle_v6_insn): Add code to handle MOVW, MOVT, QADD16, QASX, QSAX, QSUB16, QADD8, QSUB8, UADD16, USUB16, UADD8, USUB8, SEL, REV, REV16, RBIT, BFC, BFI, SBFX and UBFX instructions. (handle_VFP_move): New function. (ARMul_Emulate16): Add checks for newly supported v6 instructions. Add support for VMRS, VMOV and MRC instructions. (Multiply64): Allow nRdHi == nRm and/or nRdLo == nRm when operating in v6 mode. * armemu.h (t_resolved): Define. * armsupp.c: Include math.h. (handle_VFP_xfer): New function. Handles VMOV, VSTM, VSTR, VPUSH, VSTM, VLDM and VPOP instructions. (ARMul_LDC): Test for co-processor 10 or 11 and pass call to the new handle_VFP_xfer function. (ARMul_STC): Likewise. (handle_VFP_op): New function. Handles VMLA, VMLS, VNMLA, VNMLS, VNMUL, VMUL, VADD, VSUB, VDIV, VMOV, VABS, VNEG, VSQRT, VCMP, VCMPE and VCVT instructions. (ARMul_CDP): Test for co-processor 10 or 11 and pass call to the new handle_VFP_op function. * thumbemu.c (tBIT, tBITS, ntBIT, ntBITS): New macros. (test_cond): New function. Tests a condition and returns non-zero if the condition has been met. (handle_IT_block): New function. (in_IT_block): New function. (IT_block_allow): New function. (ThumbExpandImm): New function. (handle_T2_insn): New function. Handles T2 thumb instructions. (handle_v6_thumb_insn): Add next_instr and pc parameters. (ARMul_ThumbDecode): Add support for IT blocks. Add support for v6 instructions. * wrapper.c (sim_create_inferior): Detect a thumb address and call SETT appropriately.
2015-03-30sim: arm: delete NEED_UI_LOOP_HOOK handlingMike Frysinger1-19/+0
2015-03-30sim: arm: clean up misc warningsMike Frysinger1-1/+4
Also delete a few unused funcs.
2014-03-14Add support for instruction level tracing to the ARM simulator.Nick Clifton1-15/+38
* wrapper.c (op_print): New function. (sim_dis_read): New function. (print_insn): New function - disassembles the given instruction. (sim_trace): Note that tracing is now allowed. (sim_create_inferior): Default to emulating v6. Initialise the disassembler machinery. (sim_target_parse_command_line): Add support for -t -d and -z options. (sim_target_display_usage): Note existence of -d and -z options. (sim_open): Parse -t -d and -z options. * armemu.h: Add exports of trace, disas and trace_funcs. Add prototype for print_insn. * armemu.c (ARMul_Emulate26): Add tracing code. Delete unused variables. * thumbemu (handle_v6_thumb_insn): Delete unused variable Rd. Move Rm variable into switch cases. Add tracing code. * armcopro.c (XScale_cp15_init): Add a return value. (XScale_cp13_init): Likewise. (XScale_cp14_init): Likewise. (XScale_cp15_LDC): Delete unused function. (XScale_cp15_STC): Likewise. * maverick.c: Delete comment inside comment. (DSPInit): Delete unused function. (DSPMCR4): Fix compile time warning about missing parenthesis. (DSPMCR5): Likewise. (DSPCDP6): Delete unused variable opcode2.
2014-03-14Prevent writes to R15 via LDR or LDM from changing the ARM/Thumb state in ↵David McQuillan1-2/+14
pre-v5 architectures. PR sim/8388 * armemu.c (WriteR15Load): New function. Determines if the state can be changed upon a write to R15. (LoadMult): Use WriteR15Load. * armemu.h (WRITEDESTB): Use WriteR15Load.
2013-05-15sim: arm: add support for MOVW and MOVT instructionsMike Frysinger1-4/+8
From: Jayant R. Sonar <Jayant.Sonar@kpitcummins.com> This patch adds simulator support for handling the armv7 instructions 'movw (immediate)' and 'movt'. Compiler frequently use these instructions to load the 32bit addresses of global variables, string pointers etc. into the general registers. In absence of support of these instructions: 1. GDB run simulator fails to print even simple "hello world" string on console. 2. Loading of global variable addresses into the registers fail causing arithmetic operation failures. Patch has been regression tested for arm-none-eabi (-march=armv7-a).
2012-12-19[sim] Update old contact info in GPL license noticesJoel Brobecker1-2/+1
sim/ChangeLog: Update old contact info in GPL license notices.
2012-12-19Update sim copyright headers from GPLv2-or-later to GPLv3-or-later.Joel Brobecker1-1/+1
gdb/sim/ChangeLog: Update the non-FSF-copyrighted files in sim to GPLv3 or later.
2007-02-15* armemu.c (handle_v6_insn): Fix typo in sign extension test of the sext and ↵Nick Clifton1-1/+1
sxtah instructions.
2005-09-192005-09-19 Paul Brook <paul@codesourcery.com>Paul Brook1-26/+26
* armdefs.h: Define ARMsword and ARMsdword. Use stdint.h when available. * armemu.c: Use them. * armvirt.c (ARMul_MemoryInit): Use correct type for size. * configure.ac: Check for stdint.h. * config.in: Regenerate. * configure: Regenerate.
2005-05-12Update the address of the FSF organizationNick Clifton1-1/+1
2005-04-25* armemu.c (handle_v6_insn): New function - emulate a few of the v6 ↵Nick Clifton1-0/+295
instructions - the ones now generated by GCC. (ARMulEmulate32): Call handle_v6_insn when a possible v6 insn is found. * armdefs.h (struct ARMul_State): Add new field: is_v6.# (ARM_v6_Prop): Define. * arminit.c (ARMul_NewState): Initialise the v6 flag. (ARMul_SelectProcessor): Determine if the v6 flag should be set. * wrapper.c (sim_create_inferior): For unknown architectures, default to allowing the v6 instructions.
2004-06-29Index: mn10200/ChangeLogAndrew Cagney1-3/+3
2004-06-28 Andrew Cagney <cagney@gnu.org> * interp.c: Rename ui_loop_hook to deprecated_ui_loop_hook. Index: d10v/ChangeLog 2004-06-28 Andrew Cagney <cagney@gnu.org> * interp.c (sim_resume): Rename ui_loop_hook to deprecated_ui_loop_hook. Index: arm/ChangeLog 2004-06-28 Andrew Cagney <cagney@gnu.org> * armemu.c: Rename ui_loop_hook to deprecated_ui_loop_hook. Index: common/ChangeLog 2004-06-28 Andrew Cagney <cagney@gnu.org> * run.c: Rename ui_loop_hook to deprecated_ui_loop_hook.
2003-03-30Remove use of __IWMMXT__.Nick Clifton1-11/+3
2003-03-27Add iWMMXt support to ARM simulatorNick Clifton1-0/+27
2002-07-05Add checks to catch invaliud XScale MIA, MIAPH and MIAxy instructions.Nick Clifton1-68/+74
2002-05-27Only perform access checks if 'check' is set.Nick Clifton1-1/+1
Report unknown machine numbers. Formatting tidy ups.
2002-01-10Fix parameters passed to CPRead[13] and CPRead[14].Nick Clifton1-391/+417
2001-10-18Add support for XScale's coprocessor access check register.Nick Clifton1-444/+437
Fix formatting.
2001-05-11Fix handling of XScale LDRD and STRD instructions with post indexed ↵Nick Clifton1-6/+6
addressing modes.
2001-04-18* XScale coprocessor support.Matthew Green1-20/+87
2001-04-18 matthew green <mrg@redhat.com> * armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes. (read_cp15_reg): Make non-static. (XScale_cp15_LDC): Update for write_cp15_reg() change. (XScale_cp15_MCR): Likewise. (XScale_cp15_write_reg): Likewise. (XScale_check_memacc): New function. Check for breakpoints being activated by memory accesses. Does not support the Branch Target Buffer. (XScale_set_fsr_far): New function. Set FSR and FAR for XScale. (XScale_debug_moe): New function. Set the debug Method Of Entry, if configured. (write_cp14_reg): Reset count counter if requested. * armdefs.h (struct ARMul_State): New members `LastTime' and `CP14R0_CCD' used for the timer/counters. (ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS, ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD, ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2, ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2, ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT, ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X, ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT, ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New defines for XScale registers. (XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype. (ARMul_Emulate32, ARMul_Emulate26): Clean up function definition. (ARMul_Emulate32): Handle the clock counter and hardware instruction breakpoints. Call XScale_set_fsr_far() for software breakpoints and software interrupts. (LoadMult): Call XScale_set_fsr_far() for data aborts. (LoadSMult): Likewise. (StoreMult): Likewise. (StoreSMult): Likewise. * armemu.h (write_cp15_reg): Update prototype. * arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime. (ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13 register 0. * armvirt.c (GetWord): Call XScale_check_memacc(). (PutWord): Likewise.
2001-02-28Add support for disabling alignment checks when performing GDB interfaceNick Clifton1-2/+2
calls or SWI emulaiton routines. (Alignment checking code has not yet been contributed).
2001-02-16Remove Prefetch abort for breakpoints. Instead set the state to RESUME.Nick Clifton1-12/+2
2001-02-15Add code to preserve processor mode when a prefetchNick Clifton1-0/+11
abort is signalled after processing a breakpoint.
2001-02-01Add parentheses ready for future conbtributionNick Clifton1-39/+63
2001-02-01Update base address register after restoring register bank.Nick Clifton1-26/+57
2000-12-19Fix test for StoreDouble Instruction.Nick Clifton1-12/+12
2000-12-08oops - remove redundant prototype introduced in previous deltaNick Clifton1-2/+0
2000-12-08Add emulation of double word load and store instructions.Nick Clifton1-3/+340
2000-11-30Add support for ARM's v5TE architecture and Intel's XScale extenstionsNick Clifton1-5/+491
2000-08-15Compute write back value for post increment loads beforeNick Clifton1-34/+41
performing the load in case the offset register is overwritten.
2000-07-04* armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn.Alexandre Oliva1-1/+1
2000-07-04* armemu.h (INSN_SIZE): New macro.Alexandre Oliva1-12/+23
(SET_ABORT): Save CPSR in SPSR and set LR. * armemu.c (ARMul_Emulate, isize): Set to INSN_SIZE. (WriteR15, WriteSR15): Do not discard bit 1 in Thumb mode. * arminit.c (ARMul_Abort): Use new SETABORT and INSN_SIZE.
2000-07-04* armemu.c (LoadSMult): Use WriteR15() to discard the leastAlexandre Oliva1-2/+2
significant bits of PC.
2000-07-04* armemu.h (WRITEDESTB): New macro.Alexandre Oliva1-37/+35
* armemu.c (ARMul_Emulate26, bl): Use WriteR15Branch() to modify PC. Moved the existing logic... (WriteR15Branch): ... here. New function. (WriteR15, WriteSR15): Drop the two least significant bits. (LoadSMult): Use WriteR15Branch() to modify PC. (LoadMult): Use WRITEDESTB() instead of WRITEDEST().
2000-07-04* armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.Alexandre Oliva1-4/+4
(SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros. (SETPSR, SET_INTMODE, SETCC): Removed. * armsupp.c (ARMul_FixCPSR, ARMul_FixSPSR): Do not test bit mask. Use SETPSR_* to modify PSR. (ARMul_SetCPSR): Load all bits from value. * armemu.c (ARMul_Emulate, msr): Do not test bit mask.
2000-07-04* armemu.c (ARMul_Emulate): Compute writeback value beforeAlexandre Oliva1-8/+16
loading, since the offset register may be the destination register.
2000-06-22* armemu.c (Multiply64): Fix computation of flag N.Alexandre Oliva1-4/+3
2000-06-22* armemu.c (MultiplyAdd64): Fix computation of flag N.Alexandre Oliva1-4/+3
2000-05-30Add support for v4 SystemMode.Nick Clifton1-1/+5
2000-04-10* arm abort fixFrank Ch. Eigler1-3/+3
2000-03-11 Philip Blundell <philb@gnu.org> * armemu.c (LoadSMult, LoadMult): Correct handling of aborts. Patch from Allan Skillman <Allan.Skillman@arm.com>.
2000-02-08Fix compile time warning messages.Nick Clifton1-6/+5
2000-02-05import gdb-2000-02-04 snapshotJason Molenda1-2738/+3128
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