diff options
| author | Alexandre Oliva <aoliva@redhat.com> | 2000-07-04 06:52:30 +0000 |
|---|---|---|
| committer | Alexandre Oliva <aoliva@redhat.com> | 2000-07-04 06:52:30 +0000 |
| commit | e063aa3bd8d3712e37a287603d3256282c209def (patch) | |
| tree | 7e016132f8291cc7f4fdb5f8d129816f2e58495e /sim/arm/armemu.c | |
| parent | 13b6dd6f68d9eb79f9d3dbe730ec1b6aa9bef737 (diff) | |
| download | gdb-e063aa3bd8d3712e37a287603d3256282c209def.zip gdb-e063aa3bd8d3712e37a287603d3256282c209def.tar.gz gdb-e063aa3bd8d3712e37a287603d3256282c209def.tar.bz2 | |
* armemu.h (INSN_SIZE): New macro.
(SET_ABORT): Save CPSR in SPSR and set LR.
* armemu.c (ARMul_Emulate, isize): Set to INSN_SIZE.
(WriteR15, WriteSR15): Do not discard bit 1 in Thumb mode.
* arminit.c (ARMul_Abort): Use new SETABORT and INSN_SIZE.
Diffstat (limited to 'sim/arm/armemu.c')
| -rw-r--r-- | sim/arm/armemu.c | 35 |
1 files changed, 23 insertions, 12 deletions
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c index 43cd6dc..31bd327 100644 --- a/sim/arm/armemu.c +++ b/sim/arm/armemu.c @@ -299,14 +299,7 @@ ARMul_Emulate26 (register ARMul_State * state) do { /* just keep going */ -#ifdef MODET - if (TFLAG) - { - isize = 2; - } - else -#endif - isize = 4; + isize = INSN_SIZE; switch (state->NextInstr) { case SEQ: @@ -3104,8 +3097,15 @@ WriteR15 (ARMul_State * state, ARMword src) { /* The ARM documentation states that the two least significant bits are discarded when setting PC, except in the cases handled by - WriteR15Branch() below. */ - src &= 0xfffffffc; + WriteR15Branch() below. It's probably an oversight: in THUMB + mode, the second least significant bit should probably not be + discarded. */ +#ifdef MODET + if (TFLAG) + src &= 0xfffffffe; + else +#endif + src &= 0xfffffffc; #ifdef MODE32 state->Reg[15] = src & PCBITS; #else @@ -3122,15 +3122,26 @@ WriteR15 (ARMul_State * state, ARMword src) static void WriteSR15 (ARMul_State * state, ARMword src) { - src &= 0xfffffffc; #ifdef MODE32 - state->Reg[15] = src & PCBITS; if (state->Bank > 0) { state->Cpsr = state->Spsr[state->Bank]; ARMul_CPSRAltered (state); } +#ifdef MODET + if (TFLAG) + src &= 0xfffffffe; + else +#endif + src &= 0xfffffffc; + state->Reg[15] = src & PCBITS; #else +#ifdef MODET + if (TFLAG) + abort (); /* ARMul_R15Altered would have to support it. */ + else +#endif + src &= 0xfffffffc; if (state->Bank == USERBANK) state->Reg[15] = (src & (CCBITS | R15PCBITS)) | ER15INT | EMODE; else |