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1996-08-29 * v850-opc.c (v850_opcodes): Fix opcode specs forJeff Law2-5/+10
sld.w, sst.b, sst.h, sst.w, and nop.
1996-08-28 * v850-opc.c (v850_opcodes): Add null opcode to mark theJeff Law2-5/+31
end of the opcode table. For the simulator
1996-08-26Remove v850-opc.c from things-to-keepJ.T. Conklin1-1/+0
1996-08-23 * v850-opc.c (v850_operands): Define EP operand.Jeff Law2-5/+12
(IF4A, IF4B, IF4C, IF4D): Use EP.
1996-08-23 * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov"Jeff Law2-7/+7
with immediate operand, "movhi". Tweak "ldsr". More fixes.
1996-08-23 * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw]Jeff Law2-9/+12
correct. Get sld.[bhw] and sst.[bhw] closer.
1996-08-23 * v850-opc.c (v850_operands): "not" is a two byte insn.Jeff Law2-1/+3
1996-08-23 * v850-opc.c (v850_opcodes): Correct bit pattern for setf.Jeff Law2-1/+3
1996-08-23 * v850-opc.c (v850_operands): D16 inserts at offset 16!Jeff Law2-1/+3
1996-08-23 * v850-opc.c (two): Get order of words correct.Jeff Law2-1/+3
1996-08-23 * v850-opc.c (v850_operands): I16 inserts at offset 16!Jeff Law2-1/+3
Should get immediate 16bit operands into the right place
1996-08-23 * v850-opc.c (v850_operands): Add "SR1" and "SR2" for systemJeff Law2-2/+12
register source and destination operands. (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr". More parsing fixes.
1996-08-23 * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. FixJeff Law2-2/+3
same thinko in "trap" opcode.
1996-08-23 * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode.Jeff Law2-1/+3
1996-08-23 * v850-opc.c (v850_opcodes): Add initializer for size fieldJeff Law2-84/+87
on all opcodes.
1996-08-23 * v850-opc.c (v850_operands): D6 -> DS7. References changed.Jeff Law2-15/+29
Add D8 for 8-bit unsigned field in short load/store insns. (IF4A, IF4D): These both need two registers. (IF4C, IF4D): Define. Use 8-bit unsigned field. (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand for "ldsr" and "stsr". * v850-opc.c (v850_operands): 3-bit immediate for bit insns is unsigned. Fixing up the parser again.
1996-08-23 * v850-opc.c (v850_operansd): 3-bit immediate for bit insnsJeff Law2-1/+4
is unsigned.
1996-08-23Add V850_OPERAND_SIGNED flag as appropriate, create new unsigned IMM5 operandJ.T. Conklin1-8/+11
1996-08-23 * v850-opc.c (v850_opcodes): Correct short store half (sst.h) andJeff Law2-1/+6
short store word (sst.w).
1996-08-23start writing functions for extracting and inserting unusual operandsJ.T. Conklin1-6/+37
1996-08-23* v850-opc.c (v850_operands): Added insert and extract fields,J.T. Conklin2-15/+22
pointers to functions that handle unusual operand encodings.
1996-08-22 * v850-opc.c (v850_opcodes): Enable "trap".Jeff Law2-2/+2
1996-08-22 * v850-opc.c (v850_opcodes): Fix order of displacementJeff Law2-4/+9
and register for "set1", "clr1", "not1", and "tst1".
1996-08-22minimal setf supportJ.T. Conklin1-1/+3
1996-08-22Stub in load and store insns. Fix order of jarl operandsJ.T. Conklin1-5/+19
1996-08-22Arggh. B3. shift counts are from the start of each half-word apparently.Jeff Law1-1/+1
1996-08-22Fix thinko in B3.Jeff Law1-1/+1
1996-08-22 * v850-opc.c (v850_operands): Add "B3" support.Jeff Law2-8/+14
(v850_opcodes): Fix and enable "set1", "clr1", "not1" and "tst1".
1996-08-22 * v850-ope.c ("jmp"): R1 is only operand.Jeff Law2-1/+3
1996-08-22 * v850-opc.c: Close unterminated comment.Jeff Law2-1/+5
Something -Wall caught.
1996-08-22* v850-opc.c: Add flags field to struct v850_operands, add moveJ.T. Conklin2-22/+35
opcodes to opcode table.
1996-08-20* Makefile.in (ALL_MACHINES): Add v850-opc.o.J.T. Conklin3-0/+239
* configure: (bfd_v850v_arch) Add new case. * configure.in: (bfd_v850_arch) Add new case. * v850-opc.c: New file.
1996-08-19 * sparc-dis.c (print_insn_sparc): Handle little endian sparcs.David Edelsohn1-0/+12
1996-08-15 * mpw-make.sed: Update editing of include pathnames to beStan Shebs2-2/+13
more general.
1996-08-15Thu Aug 15 16:28:41 1996 James G. Smith <jsmith@cygnus.co.uk>Jackie Smith Cashion1-0/+1
* arm-opc.h: Added "bx" instruction definition.
1996-08-15Wed Aug 14 17:00:04 1996 Richard Henderson <rth@tamu.edu>Ian Lance Taylor1-0/+4
* alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5.
1996-08-12Mon Aug 12 14:30:37 1996 Martin M. Hunt <hunt@pizza.cygnus.com>Martin Hunt1-0/+4
* d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l.
1996-08-09Fri Aug 9 13:21:59 1996 Martin M. Hunt <hunt@pizza.cygnus.com>Martin Hunt2-2/+8
* d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER.
1996-08-08Thu Aug 8 12:43:52 1996 Klaus Kaempf <kkaempf@progis.de>Ian Lance Taylor1-0/+4
* makefile.vms: Update for alpha-opc changes.
1996-08-07 * i386-dis.c (print_insn_i386): Actually return the correct value.Ian Lance Taylor1-0/+5
(ONE, OP_ONE): #ifdef out; not used.
1996-08-03Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com>Martin Hunt2-2/+11
* d10v-opc.c (d10v_operands): Added 2 accumulator sub instructions. Changed subi operand type to treat 0 as 16.
1996-07-31 * m68k-opc.c: Add cpushl for the mcf5200. From Ken RoseIan Lance Taylor1-0/+5
<rose@netcom.com>.
1996-07-31Wed Jul 31 14:39:27 1996 James G. Smith <jsmith@cygnus.co.uk>Jackie Smith Cashion2-0/+11
* arm-opc.h: (arm_opcodes): Added halfword and sign-extension memory transfer instructions. Add new format string entries %h and %s. * arm-dis.c: (print_insn_arm): Provide decoding of the new formats %h and %s.
1996-07-26Fri Jul 26 11:45:04 1996 Martin M. Hunt <hunt@pizza.cygnus.com>Martin Hunt2-4/+13
* d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift. (d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
1996-07-26 * alpha-dis.c (print_insn_alpha_osf): Remove.Ian Lance Taylor1-0/+8
(print_insn_alpha_vms): Remove. (print_insn_alpha): Make globally visible. Chose the register names based on info->flavour. * disassemble.c: Always return print_insn_alpha for the alpha.
1996-07-25Thu Jul 25 15:24:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com>Martin Hunt1-0/+4
* d10v-dis.c (dis_long): Handle unknown opcodes.
1996-07-25Thu Jul 25 12:08:09 1996 Martin M. Hunt <hunt@pizza.cygnus.com>Martin Hunt3-43/+73
* d10v-opc.c: Changes to support signed and unsigned numbers. All instructions with the same name that have long and short forms now end in ".l" or ".s". Divs added. * d10v-dis.c: Changes to support signed and unsigned numbers.
1996-07-23start-sanitize-d10vMartin Hunt2-50/+70
Tue Jul 23 11:02:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com> * d10v-dis.c: Change all functions to use info->print_address_func. end-sanitize-d10v
1996-07-22Mon Jul 22 15:38:53 1996 Andreas Schwab ↵Ian Lance Taylor2-5/+11
<schwab@issan.informatik.uni-dortmund.de> * m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire move ccr/sr insns more strict so that the disassembler only selects them when the addressing mode is data register.
1996-07-22start-sanitize-d10vMartin Hunt3-10/+81
Mon Jul 22 11:25:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com> * d10v-opc.c (pre_defined_registers): Declare. * d10v-dis.c (print_operand): Now uses pre_defined_registers to pick a better name for the registers. end-sanitize-d10v
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