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2021-06-02arc: Construct disassembler options dynamicallyShahab Vahedi2-27/+161
2021-05-29PowerPC table driven -Mraw disassemblyAlan Modra3-1635/+1634
2021-05-29MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructionsMaciej W. Rozycki2-66/+73
2021-05-29MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki2-51/+61
2021-05-29MIPS/opcodes: Remove DMFC3 and DMTC3 instructionsMaciej W. Rozycki2-4/+5
2021-05-29MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki2-2/+8
2021-05-29MIPS/opcodes: Add legacy CP1 control register namesMaciej W. Rozycki2-25/+47
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki4-17/+39
2021-05-29MIPS/opcodes: Add TX39 CP0 register namesMaciej W. Rozycki2-1/+19
2021-05-29MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki2-4/+9
2021-05-29microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1Maciej W. Rozycki2-1/+6
2021-05-27PowerPC: Add new xxmr and xxlnot extended mnemonicsPeter Bergner2-0/+6
2021-05-25Regen cris filesAlan Modra5-30/+67
2021-05-24opcodes: cris: move desc & opc files from sim/Mike Frysinger9-4/+3403
2021-05-18RISC-V: PR27814, Objdump crashes when disassembling a non-ELF RISC-V binary.Job Noorman2-10/+20
2021-05-17arm: Fix bugs with MVE vmov from two GPRs to vector lanesAlex Coplan2-2/+14
2021-05-11Fix an illegal memory access when attempting to disassemble a corrupt TIC30 b...Nick Clifton2-0/+9
2021-05-06or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha()Stafford Horne2-1/+11
2021-05-01opcodes: xtensa: support branch visualizationMax Filippov2-0/+15
2021-04-26x86: optimize LEAJan Beulich3-2/+7
2021-04-23opcodes: xtensa: display loaded literal valueMax Filippov2-1/+24
2021-04-23opcodes: xtensa: improve literal outputMax Filippov2-0/+6
2021-04-19aarch64: New instructions for maintenance of GPT entries cached in a TLBPrzemyslaw Wirkus2-0/+10
2021-04-19aarch64: Add new data cache maintenance operationsPrzemyslaw Wirkus2-0/+7
2021-04-19arm64: add two initializersJan Beulich2-2/+8
2021-04-16aarch64: Define RME system registersPrzemyslaw Wirkus2-0/+8
2021-04-16Update the ChangeLog, and add the missing entries.Nelson Chu1-0/+5
2021-04-16RISC-V: compress "addi d,CV,z" to "c.mv d,CV"Lifang Xia1-0/+1
2021-04-13ENABLE_CHECKING in bfd, opcodes, binutils, ldAlan Modra4-2/+42
2021-04-09AArch64: Fix Atomic LD64/ST64 classification.Tejas Belagod2-4/+9
2021-04-09PowerPC disassembly of pcrel referencesAlan Modra2-10/+143
2021-04-08PR27684, PowerPC missing mfsprg0 and othersAlan Modra2-4/+10
2021-04-08PR27676, PowerPC missing extended dcbt, dcbtst mnemonicsAlan Modra2-7/+90
2021-04-06Return symbol from symbol_at_address_funcAlan Modra3-23/+14
2021-04-05C99 opcodes configuryAlan Modra8-1248/+528
2021-04-01Remove strneq macro and use startswith.Martin Liska5-18/+9
2021-04-01PR27675, PowerPC missing extended mnemonic mfummcr2Alan Modra2-0/+7
2021-03-31Use bool in opcodesAlan Modra49-1573/+1591
2021-03-31Remove bfd_stdint.hAlan Modra12-11/+25
2021-03-30x86: drop seg_entryJan Beulich3-21/+17
2021-03-30x86: drop REGNAM_{AL,AX,EAX}Jan Beulich2-5/+4
2021-03-30x86: adjust st(<N>) parsingJan Beulich4-12/+13
2021-03-29x86: move some opcode table entriesJan Beulich3-489/+500
2021-03-29x86: VPSADBW's source operands are also commutativeJan Beulich3-6/+12
2021-03-29x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich4-924/+645
2021-03-29x86: undo Prefix_0X<nn> use in opcode tableJan Beulich3-375/+383
2021-03-29x86: shrink some struct insn_template fieldsJan Beulich2-4/+10
2021-03-29x86: derive opcode encoding space attribute from base opcodeJan Beulich3-1601/+1641
2021-03-29TRUE/FALSE simplificationAlan Modra5-54/+68
2021-03-29opcodes int vs bfd_boolean fixesAlan Modra3-10/+15
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