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2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich4-3/+10
Despite SYSEXIT being an Intel-only insn in long mode, its behavior there is similar to SYSRET's: Depending on REX.W execution continues in either 64-bit or compatibility mode. Hence distinguishing by suffix is as necessary here as it is there.
2021-03-03x86: infer operand count of templatesJan Beulich3-3453/+3447
Having this count explicitly in the table is redundant and (even if just slightly) disturbs clarity. Infer the count from the number of operands actually found. Also convert the "no operands" indicator from "{ 0 }" to just "{}", as that (now) ends up being easier to parse.
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu3-32/+54
* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types, [VALID/EXTRACT/ENCODE macros] BTYPE_IMM: Renamed from SBTYPE_IMM. JTYPE_IMM: Renamed from UJTYPE_IMM. CITYPE_IMM: Renamed from RVC_IMM. CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM. CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM. CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM. CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM. CIWTYPE_IMM: Renamed from RVC_UIMM8. CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM. CSSTYPE_IMM: Added for .insn without special encoding. CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM. CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM. CLTYPE_IMM: Added for .insn without special encoding. CLTYPE_LW_IMM: Renamed from RVC_LW_IMM. CLTYPE_LD_IMM: Renamed from RVC_LD_IMM. RVC_SIMM3: Unused and removed. CBTYPE_IMM: Renamed from RVC_B_IMM. CJTYPE_IMM: Renamed from RVC_J_IMM. * Added new operands and removed the unused ones, C5: Unsigned CL(CS) immediate, added for .insn directive. C6: Unsigned CSS immediate, added for .insn directive. Ci: Unused and removed. C<: Unused and removed. bfd/ PR 27158 * elfnn-riscv.c (perform_relocation): Updated encoding macros. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. * elfxx-riscv.c (howto_table): Likewise. gas/ PR 27158 * config/tc-riscv.c (riscv_ip): Updated encoding macros. (md_apply_fix): Likewise. (md_convert_frag_branch): Likewise. (validate_riscv_insn): Likewise. Also arranged operands, including added C5 and C6 operands, and removed unused Ci and C< operands. * doc/c-riscv.texi: Updated and added CSS/CL/CS types. * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions. * testsuite/gas/riscv/insn.s: Likewise. gdb/ PR 27158 * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros. (decode_j_type_insn): Likewise. (decode_cj_type_insn): Likewise. (decode_b_type_insn): Likewise. (decode): Likewise. include/ PR 27158 * opcode/riscv.h: Updated encoding macros. opcodes/ PR 27158 * riscv-dis.c (print_insn_args): Updated encoding macros. * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. (match_c_addi16sp): Updated encoding macros. (match_c_lui): Likewise. (match_c_lui_with_hint): Likewise. (match_c_addi4spn): Likewise. (match_c_slli): Likewise. (match_slli_as_c_slli): Likewise. (match_c_slli64): Likewise. (match_srxi_as_c_srxi): Likewise. (riscv_insn_types): Added .insn css/cl/cs. sim/ PR 27158 * riscv/sim-main.c (execute_i): Updated encoding macros.
2021-02-18RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu3-95/+20
Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the spec versions stuff to bfd/cpu-riscv.h. Also move the csr stuff and ext_version_table to gas/config/tc-riscv.c for internal use. To avoid too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS macros. Therefore, assembler/dis-assembler/linker/gdb can get all spec versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff are defined there uniformly. bfd/ * Makefile.am: Added cpu-riscv.h. * Makefile.in: Regenerated. * po/SRC-POTFILES.in: Regenerated. * cpu-riscv.h: Added to support spec versions controlling. Also added extern arrays and functions for cpu-riscv.c. (enum riscv_spec_class): Define all spec classes here uniformly. (struct riscv_spec): Added for all specs. (RISCV_GET_SPEC_CLASS): Added to reduce repeated code. (RISCV_GET_SPEC_NAME): Likewise. (RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class. (RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class. (RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name. * cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec. (riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS. (riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME. (riscv_priv_specs): Moved below. (riscv_get_priv_spec_class_from_numbers): Likewise, updated. (riscv_isa_specs): Moved from include/opcode/riscv.h. * elfnn-riscv.c: Included cpu-riscv.h. (riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec. * elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h. (RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h. * elfxx-riscv.h: Removed extern functions to cpu-riscv.h. gas/ * config/tc-riscv.c: Included cpu-riscv.h. (enum riscv_csr_clas): Moved from include/opcode/riscv.h. (struct riscv_csr_extra): Likewise. (struct riscv_ext_version): Likewise. (ext_version_table): Moved from opcodes/riscv-opc.c. (default_isa_spec): Updated type to riscv_spec_class. (default_priv_spec): Likewise. (riscv_set_default_isa_spec): Updated. (init_ext_version_hash): Likewise. (riscv_init_csr_hash): Likewise, also fixed indent. include/ * opcode/riscv.h: Moved stuff and make the file tidy. opcodes/ * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. (default_priv_spec): Updated type to riscv_spec_class. (parse_riscv_dis_option): Updated. * riscv-opc.c: Moved stuff and make the file tidy.
2021-02-17read_leb128 overflow checkingAlan Modra2-6/+27
There is a tiny error left in dwarf.c:read_leb128 after Nick fixed the signed overflow problem in code I wrote. It's to do with sleb128 values that have unnecessary excess bytes. For example, -1 is represented as 0x7f, the most efficient encoding, but also as 0xff,0x7f or 0xff,0xff,0x7f and so on. None of these sequences overflow any size signed value, but read_leb128 will report an overflow given enough excess bytes. This patch fixes that problem, and since the proper test for signed values with excess bytes can easily be adapted to also test a sleb byte with just some bits that overflow the result, I changed the code to not use signed right shifts. (The C standard ISO/IEC 9899:1999 6.5.7 says signed right shifts of negative values have an implementation defined value. A long time ago I even used a C compiler for a certain microprocessor that always did unsigned right shifts. Mind you, it is very unlikely to be compiling binutils with such a compiler.) bfd/ * wasm-module.c: Guard include of limits.h. (CHAR_BIT): Provide backup define. (wasm_read_leb128): Use CHAR_BIT to size "result" in bits. Correct signed overflow checking. opcodes/ * wasm32-dis.c: Include limits.h. (CHAR_BIT): Provide backup define. (wasm_read_leb128): Use CHAR_BIT to size "result" in bits. Correct signed overflow checking. binutils/ * dwarf.c: Include limits.h. (CHAR_BIT): Provide backup define. (read_leb128): Use CHAR_BIT to size "result" in bits. Correct signed overflow checking. * testsuite/binutils-all/pr26548.s, * testsuite/binutils-all/pr26548.d, * testsuite/binutils-all/pr26548e.d: New tests. * testsuite/binutils-all/readelf.exp: Run them. (readelf_test): Drop unused "xfails" parameter. Update all uses.
2021-02-16x86: CVTPI2PD has special behaviorJan Beulich3-2/+39
CVTPI2PD with a memory operand, unlike CVTPI2PS, doesn't engage MMX logic. Therefore it - has a proper AVX equivalent (CVTDQ2PD) and hence can be subject to SSE2AVX translation and SSE checking, - should not record MMX use in the respective ELF note.
2021-02-16x86: have preprocessor expand macrosJan Beulich3-11/+11
There's no point having i386-gen's set_bitfield() to handle any aliases, now that we pass the opcode table through the C preprocessor anyway.
2021-02-15IBM Z: Implement instruction set extensionsAndreas Krebbel3-0/+35
opcodes/ * s390-mkopc.c (main): Accept arch14 as cpu string. * s390-opc.txt: Add new arch14 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH14. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch14. * doc/c-s390.texi: Document arch14 march option. * testsuite/gas/s390/s390.exp: Run the arch14 related tests. * testsuite/gas/s390/zarch-arch14.d: New test. * testsuite/gas/s390/zarch-arch14.s: New test.
2021-02-10bfd, opcodes, libctf: support --with-included-gettextNick Alcock3-2/+20
Right now, these libraries hardwire -L../intl -lintl on a few fixed platforms, which works fine on those platforms but on other platforms leads to shared libraries that lack libintl_* symbols when configured --with-included-gettext, and/or static libraries that contain libintl as *another* static library. If we instead use the LIBINTL variable defined in ../intl/config.intl, this gives us the right thing on all three classes of platform (gettext in libc, gettext in system libintl, gettext in ../intl/libintl.a).. This also means we can rip out some Darwin-specific machinery from configure.ac and also simplify the Cygwin side. This also means that the libctf testsuite (and other places that include libbfd, libopcodes or libctf) don't need to grow libintl dependencies just on account of those libraries (though they still need such dependencies if they themselves use gettext machinery). bfd/ChangeLog 2021-02-03 Nick Alcock <nick.alcock@oracle.com> * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in favour of LIBINTL. * configure: Regenerated. libctf/ChangeLog 2021-02-02 Nick Alcock <nick.alcock@oracle.com> * configure.ac (CTF_LIBADD): Remove explicit -lintl population in favour of LIBINTL. * Makefile.am (libctf_nobfd_la_LIBADD): No longer explicitly include $(LIBINTL). (check-DEJAGNU): Pass down to tests as well. * configure: Regenerated. * Makefile.in: Likewise. opcodes/ChangeLog 2021-02-04 Nick Alcock <nick.alcock@oracle.com> * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in favour of LIBINTL. * configure: Regenerated.
2021-02-08opcodes: tic54x: namespace exported variablesMike Frysinger3-8/+26
The tic54x exports some fairly generic variable names that can conflict with programs that use them, so put proper tic54x_ prefixes on all of them.
2021-02-04RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.Nelson Chu2-53/+10
bfd/ * elfxx-riscv.c (riscv_parse_prefixed_ext): Removed zb*. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Removed INSN_CLASS_ZB*. * testsuite/gas/riscv/bitmanip-insns-32.d: Removed. * testsuite/gas/riscv/bitmanip-insns-64.d: Removed. * testsuite/gas/riscv/bitmanip-insns.s: Removed. include/ * opcode/riscv-opc.h: Removed macros for zb* extensions. * opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_ZB*. opcodes/ * riscv-opc.c (MASK_RVB_IMM): Removed. (riscv_opcodes): Removed zb* instructions. (riscv_ext_version_table): Removed versions for zb*.
2021-01-26Segmentation fault i386-genAlan Modra2-0/+7
A case of inst->next being uninitialised. * i386-gen.c (parse_template): Ensure entire template_instance is initialised.
2021-01-15RISC-V: Indent and GNU coding standards tidy, also aligned the code.Nelson Chu2-710/+714
bfd/ * elfnn-riscv.c: Indent, labels and GNU coding standards tidy, also aligned the code. gas/ * config/tc-riscv.c: Indent and GNU coding standards tidy, also aligned the code. * config/tc-riscv.h: Likewise. include/ * opcode/riscv.h: Indent and GNU coding standards tidy, also aligned the code. opcodes/ * riscv-opc.c (riscv_gpr_names_abi): Aligned the code. (riscv_fpr_names_abi): Likewise. (riscv_opcodes): Likewise. (riscv_insn_types): Likewise.
2021-01-15RISC-V: Error and warning messages tidy.Nelson Chu2-1/+5
Error and warning messages usually starting with lower case letter, and without the period at the end. Besides, add the prefixed "internel:" at the beginning of the messages when they are caused internally. Also fix indents and typos. bfd/ * elfnn-riscv.c (riscv_merge_attributes): Fix typos of messages. gas/ * config/tc-riscv.c: Error and warning messages tidy. * testsuite/gas/riscv/priv-reg-fail-fext.l: Updated. * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. ld/ * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise. opcodes/ * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
2021-01-15RISC-V: Comments tidy and improvement.Nelson Chu3-32/+34
The GNU coding standards said the comments should be complete sentences and end with a period and two spaces. But sometimes it should be more cleaner when the comments only include a word or codes. Therefore, I made the following changes after referring to other target/generic codes, * Try to write sentences in comments, must end with a period and two spaces. * End with two spaces without a period for codes/instructions only. * End with one space without a period for a single word/variable only. Besids, also rewrite/remove some comments which are obsolete or too long, and fix indents for comments. bfd/ * elfnn-riscv.c: Comments tidy and improvement. * elfxx-riscv.c: Likewise. * elfxx-riscv.h: Likewise. gas/ * config/tc-riscv.c: Comments tidy and improvement. Also update comment "fallthru" to "Fall through" that end with a period and two spaces. include/ * elf/riscv.h: Comments tidy and improvement. * opcode/riscv-opc.h: Likewise. * opcode/riscv.h: Likewise. opcodes/ * riscv-dis.c: Comments tidy and improvement. * riscv-opc.c: Likewise.
2021-01-13Regen Makefile.in for jobserver.m4 aclocal.m4 dependencyAlan Modra2-0/+5
bfd/ * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. binutils/ * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. gas/ * Makefile.in: Regenerate. * Makefile.in: Regenerate. gprof/ * Makefile.in: Regenerate. ld/ * Makefile.in: Regenerate. libctf/ * Makefile.in: Regenerate. opcodes/ * Makefile.in: Regenerate.
2021-01-12Implement a workaround for GNU mak jobserverH.J. Lu4-0/+28
Compiling binutils using -flto=jobserver with GCC 11 leads to libtool: link: gcc -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Wstack-usage=262144 -Wwrite-strings -I../../gas/../zlib -g -O2 -fprofile-generate -flto=jobserver -o as-new app.o as.o atof-generic.o compress-debug.o cond.o depend.o dwarf2dbg.o dw2gencfi.o ecoff.o ehopt.o expr.o flonum-copy.o flonum-konst.o flonum-mult.o frags.o hash.o input-file.o input-scrub.o listing.o literal.o macro.o messages.o output-file.o read.o remap.o sb.o stabs.o subsegs.o symbols.o write.o config/tc-i386.o config/obj-elf.o config/atof-ieee.o ../opcodes/.libs/libopcodes.a ../bfd/.libs/libbfd.a -L/tmp/binutils-gdb/objdir/zlib -lz ../libiberty/libiberty.a -ldl lto-wrapper: warning: jobserver is not available: '--jobserver-auth=' is not present in 'MAKEFLAGS' since the '+' is missing on the recipe line in Makefiles generated by automake. Add the '+' to the recipe line by hand. bfd/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. binutils/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. config/ PR binutils/26792 * jobserver.m4: New file. gas/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. gprof/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. ld/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. libctf/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. opcodes/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise.
2021-01-12Updated translations for some subdirectoriesNick Clifton2-237/+282
2021-01-11Binutils: Check if AR works with --plugin and rcH.J. Lu2-3/+16
Check if AR works with --plugin and rc before passing --plugin to AR and RANLIB. bfd/ PR ld/27173 binutils/ PR ld/27173 * configure: Regenerated. gas/ PR ld/27173 * configure: Regenerated. gprof/ PR ld/27173 * configure: Regenerated. ld/ PR ld/27173 * configure: Regenerated. libctf/ PR ld/27173 * configure: Regenerated. opcodes/ PR ld/27173 * configure: Regenerated.
2021-01-11aarch64: Remove support for CSREKyrylo Tkachov6-1433/+1433
This patch removes support for the CSRE extension from aarch64 gas/objdump. CSRE (FEAT_CSRE) is part of the Future Architecture Technologies program and at this time Arm is withdrawing this particular feature. The patch removes the system registers and the CSR PDEC instruction. gas/ChangeLog * NEWS: Remove CSRE. * config/tc-aarch64.c (parse_csr_operand): Delete. (parse_operands): Delete handling of AARCH64_OPND_CSRE_CSR. (aarch64_features): Remove csre. * doc/c-aarch64.texi: Remove CSRE. * testsuite/gas/aarch64/csre.d: Delete. * testsuite/gas/aarch64/csre-invalid.s: Likewise. * testsuite/gas/aarch64/csre-invalid.d: Likewise. * testsuite/gas/aarch64/csre_csr.s: Likewise. * testsuite/gas/aarch64/csre_csr.d: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.s: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.l: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.d: Likewise. include/ChangeLog * opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete. (aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-opc.c (aarch64_print_operand): Delete handling of AARCH64_OPND_CSRE_CSR. * aarch64-tbl.h (aarch64_feature_csre): Delete. (CSRE): Likewise. (_CSRE_INSN): Likewise. (aarch64_opcode_table): Delete csr.
2021-01-11Updated translations for multiple subdirectoriesNick Clifton6-1234/+1453
2021-01-09Binutils: Pass --plugin to AR and RANLIBH.J. Lu2-2/+29
Detect GCC LTO plugin. Pass --plugin to AR and RANLIB to support LTO build. bfd/ * configure: Regenerated. binutils/ * configure: Regenerated. gas/ * configure: Regenerated. gprof/ * configure: Regenerated. ld/ * configure: Regenerated. libctf/ * configure: Regenerated. opcodes/ * configure: Regenerated.
2021-01-09Change version number to 2.36.50 and regenerate filesNick Clifton3-242/+288
2021-01-09Add Changelog entries and NEWS entries for 2.36 branchNick Clifton1-0/+4
2021-01-09POWER10: Add Return-Oriented Programming instructionsPeter Bergner2-1/+51
POWER10 adds some return-oriented programming (ROP) instructions and this patch adds support for them. You will notice that they are enabled for POWER8 and later, not just POWER10 and later. This is on purpose. This allows the instructions to be added to POWER8 binaries that can be run on POWER8, POWER9 and POWER10 cpus. On POWER8 and POWER9, these instructions just act as nop's. opcodes/ * ppc-opc.c (insert_dw, (extract_dw): New functions. (DW, (XRC_MASK): Define. (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics. gas/ * testsuite/gas/ppc/rop-checks.d, * testsuite/gas/ppc/rop-checks.l, * testsuite/gas/ppc/rop-checks.s, * testsuite/gas/ppc/rop.d, * testsuite/gas/ppc/rop.s: New tests. * testsuite/gas/ppc/ppc.exp: Run them.
2021-01-09configure regenAlan Modra2-2/+6
commit f478212851 did the regen by hand, missed a change in ld/configure and didn't update line numbers. Fix that, and an old regen of ld/Makefile.in with the wrong automake. bfd/ * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * Makefile.in: Regenerate. * configure: Regenerate. libctf/ * configure: Regenerate. opcodes/ * configure: Regenerate. zlib/ * configure: Regenerate.
2021-01-08Updated Swedish translation for the opcodes/ subdirectoryNick Clifton2-280/+353
2021-01-08Fix places in the AArch64 opcodes library code where a call to assert() has ↵Nick Clifton3-7/+16
side effects. PR 27129 * aarch64-dis.c (determine_disassembling_preference): Move call to aarch64_match_operands_constraint outside of the assertion. * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert. Replace with a return of FALSE.
2021-01-08Treat the AArch64 register id_aa64mmfr2_el1 as a core system register.Nick Clifton2-1/+7
PR 27139 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a core system register.
2021-01-07libtool.m4: update GNU/Hurd test from upstream. In upstream libtool, ↵Samuel Thibault2-11/+5
47a889a4ca20 ("Improve GNU/Hurd support.") fixed detection of shlibpath_overrides_runpath, thus avoiding unnecessary relink. This backports it. . * libtool.m4: Match gnu* along other GNU systems. */ChangeLog: * configure: Re-generate.
2021-01-07Updated French translation for the opcodes/ subdirectory.Nick Clifton2-242/+317
2021-01-07m68k: Require m68020up rather than m68000up for CHK.L instruction.Fredrik Noring2-1/+6
* m68k-opc.c (chkl): Change minimum architecture requirement to m68020.
2021-01-07RISC-V: Add pause hint instruction.Philipp Tomsich2-0/+7
Add support for the pause hint instruction, as specified in the Zihintpause extension. The pause instruction is encoded as a special form of a memory fence (which is available as part of the base instruction set). The chosen encoding does not mandate any particular memory ordering and therefore is a true hint. bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Added INSN_CLASS_ZIHINTPAUSE. * testsuite/gas/riscv/pause.d: New testcase. Adding coverage for the pause hint instruction. * testsuite/gas/riscv/pause.s: Likewise. include/ * opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN for pause hint instruction. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE. opcodes/ * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
2021-01-07RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).Claire Xenia Wolf2-4/+63
In fact rev8/orc.b/zext.h are the aliases of grevi/gorci/pack[w], so we should update them to INSN_ALIAS when we have supported their true instruction in the future. Though we still use the [MATCH|MAKS]_[GREVI|GORCI|PACK|PACKW] to encode them. Besides, the orc.b has the same encoding both in rv32 and rv64, so we just keep one of them in the opcode table. This patch is implemented according to the following link, https://github.com/riscv/riscv-bitmanip/pull/101 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com> Jim Wilson <jimw@sifive.com> Andrew Waterman <andrew@sifive.com> Maxim Blinov <maxim.blinov@embecosm.com> Kito Cheng <kito.cheng@sifive.com> Nelson Chu <nelson.chu@sifive.com> bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zba, zbb and zbc. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*. (riscv_get_default_ext_version): Do not check the default_isa_spec when the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT. * testsuite/gas/riscv/bitmanip-insns-32.d: New testcase. * testsuite/gas/riscv/bitmanip-insns-64.d: Likewise. * testsuite/gas/riscv/bitmanip-insns.s: Likewise. include/ * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for ZBA/ZBB/ZBC. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZB*. (enum riscv_isa_spec_class): Added ISA_SPEC_CLASS_DRAFT for the frozen extensions. opcodes/ * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions. (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
2021-01-01PR27116, Spelling errors found by Debian style checkerAlan Modra1-1/+1
PR 27116 bfd/ * xcofflink.c: Correct spelling in comments. binutils/ * coffgrok.c (do_type): Correct spelling of auxiliary in errors. * doc/binutils.texi: Correct grammar. * readelf.c (process_version_sections): Correct spelling of auxiliary in warning. * testsuite/binutils-all/vax/objdump.exp: Comment grammar fix. config/ * override.m4: Correct comment grammar. gas/ * config/tc-i386.c: Correct comment spelling. * config/tc-riscv.c: Likewise. * config/tc-s390.c: Correct comment grammar. * doc/c-i386.texi: Correct spelling. * doc/c-s390.texi: Correct grammar. gold/ * tilegx.cc: Correct comment spelling. gprof/ * README: Correct grammar. * gprof.texi: Likewise. include/ * coff/internal.h: Correct comment spelling. * coff/sym.h: Likewise. * opcode/aarch64.h: Likewise. ld/ * configure.tgt: Correct comment grammar. * emultempl/m68hc1xelf.em: Likewise. * ld.texi: Correct grammar.
2021-01-01Update year range in copyright notice of binutils filesAlan Modra276-279/+283
2021-01-01ChangeLog rotationAlan Modra2-3269/+3283
2020-12-10RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.Nelson Chu2-0/+9
https://github.com/riscv/riscv-asm-manual/pull/61 We aleady have sext.w, so just add sext.b, sext.h, zext.b, zext.h and zext.w. In a certain sense, zext.b is not a pseudo - It is an alias of andi. Similarly, sext.b and sext.h are aliases of other rvb instructions, when we enable b extension; But they are pseudos when we just enable rvi. However, this patch does not consider the rvb cases. Besides, zext.w is only valid in rv64. gas/ * config/tc-riscv.c (riscv_ext): New function. Use md_assemblef to expand the zext and sext pseudos, to give them a chance to be expanded into c-ext instructions. (macro): Handle M_ZEXTH, M_ZEXTW, M_SEXTB and M_SEXTH. * testsuite/gas/riscv/ext.s: New testcase. * testsuite/gas/riscv/ext-32.d: Likewise. * testsuite/gas/riscv/ext-64.d: Likewise. include/ * opcode/riscv.h (M_ZEXTH, M_ZEXTW, M_SEXTB, M_SEXTH.): Added. opcodes/ * riscv-opc.c (riscv_opcodes): Add sext.[bh] and zext.[bhw].
2020-12-10RISC-V: Dump CSR according to the elf privileged spec attributes.Nelson Chu4-4/+47
opcodes/ * disassemble.h (riscv_get_disassembler): Declare. * disassemble.c (disassembler): Changed to riscv_get_disassembler. * riscv-dis.c (riscv_get_disassembler): Check the elf privileged spec attributes before calling print_insn_riscv. (parse_riscv_dis_option): Same as the assembler, the priority of elf attributes are higher than the options. If we find the privileged attributes, but the -Mpriv-spec= is different, then output error/warning and still use the elf attributes set.
2020-12-10RISC-V: Control fence.i and csr instructions by zifencei and zicsr.Nelson Chu2-20/+25
bfd/ * elfxx-riscv.c (riscv_ext_dont_care_version): New function. Return TRUE if we don't care the versions of the extensions. These extensions are added to the subset list for special purposes, with the explicit versions or the RISCV_UNKNOWN_VERSION versions. (riscv_parse_add_subset): If we do care the versions of the extension, and the versions are unknown, then report errors for the non-implicit extensions, and return directly for the implicit one. (riscv_arch_str1): Do not output i extension after e, and the extensions which versions are unknown. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI. * testsuite/gas/riscv/march-imply-i.s: New testcase. * testsuite/gas/riscv/march-imply-i2p0-01.d: New testcase. The version of i is less than 2.1, and zi* are supported in the chosen spec, so enable the fence.i and csr instructions, also output the implicit zi* to the arch string. * testsuite/gas/riscv/march-imply-i2p0-02.d: Likewise, but the zi* are not supported in the spec 2.2. Enable the related instructions since i's version is less than 2.1, but do not output them. * testsuite/gas/riscv/march-imply-i2p1-01.d: New testcase. The version of i is 2.1, so don't add it's implicit zi*, and disable the related instructions. * testsuite/gas/riscv/march-imply-i2p1-01.l: Likewise. * testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise, and set the zi* explicitly, so enable the related instructions. * testsuite/gas/riscv/march-imply-i2p0.d: Removed. * testsuite/gas/riscv/march-imply-i2p1.d: Removed. include/ * opcode/riscv.h: Add INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI. opcodes/ * riscv-opc.c (riscv_opcodes): Control fence.i and csr instructions by zifencei and zicsr.
2020-12-04IBM Z: Add risbgz and risbgnz extended mnemonicsAndreas Krebbel3-12/+25
These two extended mnemonics are documented in the Principles of Operations manual but currently not supported by Binutils. They provide aliases for already supported instructions with the zero flag being set. The flag otherwise is mingled into one of the immediate operands what makes asm code much harder to read. opcodes/ * s390-opc.txt: Add risbgz and risbgnz. * s390-opc.c (U6_26): New operand type. (INSTR_RIE_RRUUU2, MASK_RIE_RRUUU2): New instruction format and mask. gas/ * testsuite/gas/s390/zarch-z10.s: Add tests for risbgz. * testsuite/gas/s390/zarch-z10.d: Add regexp for risbgz. * testsuite/gas/s390/zarch-zEC12.s: Add tests for risbgnz. * testsuite/gas/s390/zarch-zEC12.d: Add regexp for risbgnz.
2020-12-03IBM Z: Add support for HLASM extended mnemonicsAndreas Krebbel2-0/+18
Add extended mnemonics used in the HLASM assembler. All of them are just aliases for instructions we already support and help when assembling code which was written for the HLASM assembler. The HLASM mnemonics are documented here: https://www.ibm.com/support/knowledgecenter/SSENW6_1.6.0/com.ibm.hlasm.v1r6.asm/asmr1023.pdf See the 'Branching with extended mnemonic codes' chapter. objdump will still print the existing mnemonics with the exception of relative nop branches (i.e. conditional branches with an empty condition code mask). Now we have jnop and jgnop which will be used by objdump when possible. The same change have been applied to the LLVM assembler: https://reviews.llvm.org/D92185 opcodes/ * s390-opc.txt: Add extended mnemonics. gas/ * testsuite/gas/s390/esa-g5.s: Test new extended mnemonics. * testsuite/gas/s390/esa-g5.d: Likewise. * testsuite/gas/s390/esa-z900.s: Likewise. * testsuite/gas/s390/esa-z900.d: Likewise. * testsuite/gas/s390/zarch-z900.s: Likewise. * testsuite/gas/s390/zarch-z900.d: Likewise. ld/ * testsuite/ld-s390/tlsbin_64.dd: The newly added jgnop mnemonic replaces long relative branches with empty condition code mask.
2020-12-01RISC-V: Remove the unimplemented extensions.Nelson Chu2-11/+5
Although spec had defined and ratified p, v and n extensions, but we don't have any related implementaitons so far, so keep them in the supported extension table looks weird. Remove them until we have the related implementations. opcodes/ * riscv-opc.c (riscv_ext_version_table): Remove the p, v, n and their versions.
2020-12-01RISC-V: Add zifencei and prefixed h class extensions.Nelson Chu2-0/+7
bfd/ * elfxx-riscv.c (riscv_parse_std_ext): Stop parsing standard extensions when parsed h keyword. (riscv_get_prefix_class): Support prefixed h class. (riscv_std_h_ext_strtab): Likewise. (riscv_ext_h_valid_p): Likewise. (parse_config): Likewise. (riscv_std_z_ext_strtab): Add zifencei. * elfxx-riscv.h (riscv_isa_ext_class): Add RV_ISA_CLASS_H. gas/ * testsuite/gas/riscv/march-fail-order-z.d: New testcase, check orders of prefixed z extensions. * testsuite/gas/riscv/march-fail-order-z.l: Likewise. * testsuite/gas/riscv/march-fail-single-char-h.d: New testcase. * testsuite/gas/riscv/march-fail-single-char.l: Updated. * testsuite/gas/riscv/march-fail-unknown-h.d: New testcase. * testsuite/gas/riscv/march-fail-unknown.l: Updated. opcodes/ * riscv-opc.c (riscv_ext_version_table): Add zifencei.
2020-11-29x86: Do not dump DS/CS segment overrides for branch hintsBorislav Petkov2-2/+16
The previous change "x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit mode" to ignore segment override prefixes in 64-bit mode lead to dumping branch hints as excessive prefixes: ffffffff8109d5a0 <vmx_get_rflags>: ... ffffffff8109d601: 3e 77 0a ds ja,pt ffffffff8109d60e <vmx_get_rflags+0x6e> ^^^^^ In this particular case, those prefixes are not excessive but are used to provide branch hints - taken/not-taken - to the CPU. Assign active_seg_prefix in that particular case to consume them. gas/ 2002-11-29 Borislav Petkov <bp@suse.de> * testsuite/gas/i386/branch.d: Add new branch insns test. * testsuite/gas/i386/branch.s: Likewise. * testsuite/gas/i386/i386.exp: Insert the new branch test. * testsuite/gas/i386/x86-64-branch.d: Test for branch hints insns. * testsuite/gas/i386/x86-64-branch.s: Likewise. * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise. opcodes/ 2020-11-28 Borislav Petkov <bp@suse.de> * i386-dis.c (print_insn): Set active_seg_prefix for branch hint insns to not dump branch hint prefixes 0x2E and 0x3E as unused prefixes.
2020-11-16aarch64: Extract Condition flag manipulation feature from Armv8.4-APrzemyslaw Wirkus2-4/+16
Extract FLAGM (Condition flag manipulation) feature from Armv8.4-A. Please note that FLAGM stays a Armv8.4-A feature but now can be assigned to other architectures or CPUs. New -march option +flagm is added to enable independently this feature.
2020-11-14x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit modeBorislav Petkov2-5/+27
"In 64-bit mode, the CS, DS, ES, and SS segment-override prefixes have no effect. These four prefixes are not treated as segment-override prefixes for the purposes of multiple-prefix rules. Instead, they are treated as null prefixes." (AMD APM v2). However, objdump disassembles instructions containing those ignored prefixes by still generating that segment override: 66 66 2e 0f 1f 84 00 data16 nopw %cs:0x0(%rax,%rax,1) 00 00 00 00 Print those segment override prefixes as excessive ones: 66 66 2e 0f 1f 84 00 data16 cs nopw 0x0(%rax,%rax,1) 00 00 00 00 which is what they actually are - they have no effect and the decoding hardware ignores them. gas/ 2020-11-14 Borislav Petkov <bp@suse.de> * testsuite/gas/i386/x86-64-segovr.d: Adjust regexes. * testsuite/gas/i386/x86-64-nops.d: Likewise. * testsuite/gas/i386/x86-64-nops-1.d: Likewise. * testsuite/gas/i386/x86-64-nops-1-g64.d: Likewise. * testsuite/gas/i386/x86-64-nops-1-core2.d: Likewise. * testsuite/gas/i386/x86-64-nops-1-k8.d: Likewise. * testsuite/gas/i386/x86-64-nops-2.d: Likewise. * testsuite/gas/i386/x86-64-nops-3.d: Likewise. * testsuite/gas/i386/x86-64-nops-4.d: Likewise. * testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise. * testsuite/gas/i386/x86-64-nops-4-k8.d: Likewise. * testsuite/gas/i386/x86-64-nops-5.d: Likewise. * testsuite/gas/i386/x86-64-nops-5-k8.d: Likewise. * testsuite/gas/i386/x86-64-nops-7.d: Likewise. * testsuite/gas/i386/x86-64-nop-1.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-2c.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-6.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-7.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-8.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-1.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-2.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-3.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-4.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-5.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops.d:: Likewise. ld/ 2020-11-14 Borislav Petkov <bp@suse.de> * testsuite/ld-x86-64/pe-x86-64-4.od: Adjust regexes. * testsuite/ld-x86-64/tlsld3.dd: Likewise. * testsuite/ld-x86-64/tlsld4.dd: Likewise. opcodes/ 2020-11-14 Borislav Petkov <bp@suse.de> * i386-dis.c (ckprefix): Do not assign active_seg_prefix in 64-bit addressing mode. (NOTRACK_Fixup): Test prefixes for PREFIX_DS, instead of active_seg_prefix.
2020-11-11aarch64: Allow LS64 feature with Armv8.6Przemyslaw Wirkus2-1/+5
Allow users to use LS64 extension with Armv8.6 architecture.
2020-11-09Add support for the LMBD (left-most bit detect) instruction to the PRU ↵Spencer E. Olson2-0/+7
assembler. include * opcode/pru.h: Add LMBD (left-most bit detect) opcode index opcodes * pru-opc.c: Add opcode description for LMBD (left-most bit detect) gas * testsuite/gas/pru/misc.s: Add tests for lmbd (left-most bit detect) * testsuite/gas/pru/misc.d: Add tests for lmbd (left-most bit
2020-11-09aarch64: Update LS64 feature with system registerPrzemyslaw Wirkus2-0/+6
This patch: + Adds new ACCDATA_EL1 (Accelerator Data) system register, see [0]. + Adds LS64 instruction tests. + Update LS64 feature test with new register. + Fix comment for AARCH64_OPND_Rt_LS64. [0] https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/accdata_el1 Note: as this is register only extension we do not want to hide these registers behind -march flag going forward (they should be enabled by default).
generated by cgit v1.1 at 2024-11-18 23:25:54 +0000