| Age | Commit message (Collapse) | Author | Files | Lines |
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Bit 7 of BXNS is a fixed bit which distinguish it from BLXNS. Yet it is
not set in the disassembler entry mask. This commit fixes that.
2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
opcodes/
* arm-dis.c (thumb_opcodes): Fix BXNS mask.
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incompatible function types.
PR 22823
bfd Fix compile time warnings generated by gcc version 8.
* libbfd-in.h: Remove extraneous text from prototypes.
Add prototypes for bfd_false_any, bfd_true_any,
bfd_nullvoidptr_any, bfd_0_any, bfd_0u_any, bfd_0l_any,
bfd_n1_any, bfd_void_any.
(_bfd_generic_bfd_copy_private_bfd_data): Use vararg based dummy
function.
(_bfd_generic_bfd_merge_private_bfd_data): Likewise.
(_bfd_generic_bfd_set_private_flags): Likewise.
(_bfd_generic_bfd_copy_private_section_data): Likewise.
(_bfd_generic_bfd_copy_private_symbol_data): Likewise.
(_bfd_generic_bfd_copy_private_header_data): Likewise.
(_bfd_generic_bfd_print_private_bfd_data): Likewise.
(_bfd_noarchive_construct_extended_name_table): Likewise.
(_bfd_noarchive_truncate_arname): Likewise.
(_bfd_noarchive_write_ar_hdr): Likewise.
(_bfd_noarchive_get_elt_at_index): Likewise.
(_bfd_nosymbols_canonicalize_symtab): Likewise.
(_bfd_nosymbols_print_symbol): Likewise.
(_bfd_nosymbols_get_symbol_info): Likewise.
(_bfd_nosymbols_get_symbol_version_string): Likewise.
(_bfd_nosymbols_bfd_is_local_label_name): Likewise.
(_bfd_nosymbols_bfd_is_target_special_symbol): Likewise.
(_bfd_nosymbols_get_lineno): Likewise.
(_bfd_nosymbols_find_nearest_line): Likewise.
(_bfd_nosymbols_find_line): Likewise.
(_bfd_nosymbols_find_inliner_info): Likewise.
(_bfd_nosymbols_bfd_make_debug_symbol): Likewise.
(_bfd_nosymbols_read_minisymbols): Likewise.
(_bfd_nosymbols_minisymbol_to_symbol): Likewise.
(_bfd_norelocs_bfd_reloc_type_lookup): Likewise.
(_bfd_norelocs_bfd_reloc_name_lookup): Likewise.
(_bfd_nowrite_set_arch_mach): Likewise.
(_bfd_nowrite_set_section_contents): Likewise.
(_bfd_nolink_sizeof_headers): Likewise.
(_bfd_nolink_bfd_get_relocated_section_contents): Likewise.
(_bfd_nolink_bfd_relax_section): Likewise.
(_bfd_nolink_bfd_gc_sections): Likewise.
(_bfd_nolink_bfd_lookup_section_flags): Likewise.
(_bfd_nolink_bfd_merge_sections): Likewise.
(_bfd_nolink_bfd_is_group_section): Likewise.
(_bfd_nolink_bfd_discard_group): Likewise.
(_bfd_nolink_bfd_link_hash_table_create): Likewise.
(_bfd_nolink_bfd_link_add_symbols): Likewise.
(_bfd_nolink_bfd_link_just_syms): Likewise.
(_bfd_nolink_bfd_copy_link_hash_symbol_type): Likewise.
(_bfd_nolink_bfd_final_link): Likewise.
(_bfd_nolink_bfd_link_split_section): Likewise.
(_bfd_nolink_section_already_linked): Likewise.
(_bfd_nolink_bfd_define_common_symbol): Likewise.
(_bfd_nolink_bfd_define_start_stop): Likewise.
(_bfd_nodynamic_canonicalize_dynamic_symtab): Likewise.
(_bfd_nodynamic_get_synthetic_symtab): Likewise.
(_bfd_nodynamic_get_dynamic_reloc_upper_bound _bfd_): Likewise.
(_bfd_nodynamic_canonicalize_dynamic_reloc): Likewise.
* libbfd.c (bfd_false_any): New function. Like bfd_false but
accepts one or more arguments.
(bfd_true_any): Likewise.
(bfd_nullvoidptr_any): Likewise.
(bfd_0_any): Likewise.
(bfd_0u_any): Likewise.
(bfd_0l_any): Likewise.
(_bfd_n1_any): Likewise.
(bfd_void_any): Likewise.
* libbfd.h (extern): Regenerate
* aout-target.h (MY_bfd_is_target_special_symbol): Use vararg
based dummy function.
* aout-tic30.c (tic30_aout_set_arch_mach): Likewise.
* binary.c (binary_get_symbol_info): Likewise.
* coff-alpha.c (alpha_ecoff_backend_data): Likewise.
* coff-mips.c (mips_ecoff_backend_data): Likewise.
* coffcode.h (coff_set_alignment_hook): Likewise.
(symname_in_debug_hook): Likewise.
(bfd_coff_backend_data bigobj_swap_table): Likewise.
* elf-m10300.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-cr16.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-lm32.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-m32r.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-metag.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-score.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-score7.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-xstormy16.c (elf_backend_omit_section_dynsym): Likewise.
* elf32-xtensa.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-alpha.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-hppa.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-ia64-vms.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-mmix.c (elf_backend_omit_section_dynsym): Likewise.
* elf64-sh64.c (elf_backend_omit_section_dynsym): Likewise.
* elfnn-ia64.c (elf_backend_omit_section_dynsym): Likewise.
* elfxx-target.h (bfd_elfNN_bfd_debug_info_accumulate): Likewise.
(bfd_elfNN_bfd_make_debug_symbol): Likewise.
(bfd_elfNN_bfd_merge_private_bfd_data): Likewise.
(bfd_elfNN_bfd_set_private_flags): Likewise.
(bfd_elfNN_bfd_is_target_special_symbol): Likewise.
(elf_backend_init_index_section): Likewise.
(elf_backend_allow_non_load_phdr): Likewise.
* elfxx-x86.h (elf_backend_omit_section_dynsym): Likewise.
* i386msdos.c (msdos_bfd_is_target_special_symbol): Likewise.
* ieee.c (ieee_construct_extended_name_table): Likewise.
(ieee_write_armap): Likewise.
(ieee_write_ar_hdr): Likewise.
(ieee_bfd_is_target_special_symbol): Likewise.
* ihex.c (ihex_canonicalize_symtab): Likewise.
(ihex_bfd_is_target_special_symbol): Likewise.
* libaout.h (aout_32_bfd_is_target_special_symbol): Likewise.
* libecoff.h (_bfd_ecoff_bfd_is_target_special_symbol): Likewise.
(_bfd_ecoff_set_alignment_hook): Likewise.
* mach-o-target.c (bfd_mach_o_bfd_is_target_special_symbol): Likewise.
* mmo.c (mmo_bfd_is_target_special_symbol): Likewise.
* nlm-target.h (nlm_bfd_is_target_special_symbol): Likewise.
* oasys.c (oasys_construct_extended_name_table): Likewise.
(oasys_write_armap): Likewise.
(oasys_write_ar_hdr): Likewise.
(oasys_bfd_is_target_special_symbol): Likewise.
* pef.c (bfd_pef_bfd_is_target_special_symbol): Likewise.
* plugin.c (bfd_plugin_bfd_is_target_special_symbol): Likewise.
* ppcboot.c (ppcboot_bfd_is_target_special_symbol): Likewise.
* som.c (som_bfd_is_target_special_symbol): Likewise.
* srec.c (srec_bfd_is_target_special_symbol): Likewise.
* tekhex.c (tekhex_bfd_is_target_special_symbol): Likewise.
* verilog.c (verilog_bfd_is_target_special_symbol): Likewise.
* versados.c (versados_bfd_is_target_special_symbol): Likewise.
(versados_bfd_reloc_name_lookup): Likewise.
* vms-alpha.c (vms_bfd_is_target_special_symbol): Likewise.
(vms_bfd_define_start_stop): Likewise.
(alpha_vms_bfd_is_target_special_symbol): Likewise.
* wasm-module.c (wasm_bfd_is_target_special_symbol): Likewise.
* xsym.c (bfd_sym_bfd_is_target_special_symbol): Likewise.
* elf32-arc.c (get_replace_function): Assign replacement function
to func pointer.
* elf32-i370.c (i370_noop): Update prototype.
gas * config/obj-elf.c (elf_pseudo_table): Remove now redundant
casts.
(obj_elf_vtable_inherit): Rename to obj_elf_get_vtable_inherit.
(obj_elf_vtable_inherit): New stub function that calls
obj_elf_get_vtable_inherit.
(obj_elf_vtable_entry): Rename to obj_elf_get_vtable_entry.
(obj_elf_vtable_entry): New stub function that calls
obj_elf_get_vtable_entry.
* config/obj-elf.h (obj_elf_vtable_inherit): Update prototype.
(obj_elf_vtable_entry) Likewise.
(obj_elf_get_vtable_inherit) Likewise.
(obj_elf_get_vtable_entry) Likewise.
* config/tc-arm.c (md_pseudo_table): Remove now redundant cast.
* config/tc-i386c (md_pseudo_table): Likewise.
* config/tc-hppa.c (pa_vtable_entry): Call
obj_elf_get_vtable_entry.
(pa_vtable_inherit): Call obj_elf_get_vtable_inherit.
* config/tc-mips.c (s_mips_file): Replace call to dwarf2_get_file
with call to dwarf2_get_filename.
* dwarf2dbg.c (dwarf2_directive_file): Rename to
dwarf2_directive_filename.
(dwarf2_directive_file): New stub function that calls
dwarf2_directive_filename.
* dwarf2dbg.h: Prototype dwarf2_directive_filename.
opcodes * metag-dis.c (print_fmmov): Double buffer size to avoid warning
about truncation of printing.
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Remove `-Wshadow' compilation errors:
cc1: warnings being treated as errors
.../bfd/wasm-module.c: In function 'wasm_scan_name_function_section':
.../bfd/wasm-module.c:312: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
.../bfd/wasm-module.c: In function 'wasm_register_section':
.../bfd/wasm-module.c:494: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
.../bfd/wasm-module.c: In function 'wasm_compute_custom_section_file_position':
.../bfd/wasm-module.c:523: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
and:
cc1: warnings being treated as errors
.../opcodes/wasm32-dis.c: In function 'print_insn_wasm32':
.../opcodes/wasm32-dis.c:272: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
make[4]: *** [wasm32-dis.lo] Error 1
which for versions of GCC before 4.8 prevent support for the WebAssembly
target from being built. See also GCC PR c/53066.
bfd/
* wasm-module.c (wasm_scan_name_function_section): Rename
`index' local variable to `idx'.
opcodes/
* wasm32-dis.c (print_insn_wasm32): Rename `index' local
variable to `function_index'.
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The instruction encoding for the MIPS r6 sigrie instruction seems to be
incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp,
and dvp), but should be 0x0417xxxx. See ISA reference[1][2].
References:
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies, Inc., Document
Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32
REGIMM Encoding of rt Field", p. 452
[2] "MIPS Architecture For Programmers Volume II-A: The MIPS64
Instruction Set Reference Manual", Imagination Technologies, Inc.,
Document Number: MD00087, Revision 6.06, December 15, 2016, Table
A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581
opcodes/
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
gas/
* testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likewise.
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Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
This patch enables Intel PCONFIG instruction.
gas/
* config/tc-i386.c (cpu_arch): Add .pconfig.
* doc/c-i386.texi: Document .pconfig.
* testsuite/gas/i386/i386.exp: Add PCONFIG tests.
* testsuite/gas/i386/pconfig-intel.d: New test.
* testsuite/gas/i386/pconfig.d: Likewise.
* testsuite/gas/i386/pconfig.s: Likewise.
* testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise.
* testsuite/gas/i386/x86-64-pconfig.d: Likewise.
* testsuite/gas/i386/x86-64-pconfig.s: Likewise.
opcodes/
* i386-dis.c (enum): Add pconfig.
* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
(cpu_flags): Add CpuPCONFIG.
* i386-opc.h (enum): Add CpuPCONFIG.
(i386_cpu_flags): Add cpupconfig.
* i386-opc.tbl: Add PCONFIG instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
This patch enables Intel WBNOINVD instruction.
gas/
* config/tc-i386.c (cpu_arch): Add .wbnoinvd.
* doc/c-i386.texi: Document .wbnoinvd.
* testsuite/gas/i386/i386.exp: Add WBNOINVD tests.
* testsuite/gas/i386/wbnoinvd-intel.d: New test.
* testsuite/gas/i386/wbnoinvd.d: Likewise.
* testsuite/gas/i386/wbnoinvd.s: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F09.
* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
(cpu_flags): Add CpuWBNOINVD.
* i386-opc.h (enum): Add CpuWBNOINVD.
(i386_cpu_flags): Add cpuwbnoinvd.
* i386-opc.tbl: Add WBNOINVD instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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gas/
* config/tc-riscv.c (validate_riscv_insn) <'z'>: New.
(riscv_ip) <'z'>: New.
opcodes/
* riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
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The latest specification for Intel CET technology defined two
new bits instead of previously used CET bit. These are IBT and
SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits.
gas/
* config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
(cpu_noarch): Add noibt, noshstk.
(parse_insn): Change cpucet to cpuibt.
* doc/c-i386.texi: Delete .cet. Add .ibt, .shstk.
* testsuite/gas/i386/cet-ibt-inval.l: New test.
* testsuite/gas/i386/cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/cet-shstk-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise.
opcodes/
* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS,
CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
(cpu_flags): Add CpuIBT, CpuSHSTK.
* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
(i386_cpu_flags): Add cpuibt, cpushstk.
* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
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ld * po/pt_BR.po: Updated Brazilian Portugese translation.
opcodes * po/pt_BR.po: Updated Brazilian Portugese translation.
* po/de.po: Updated German translation.
gas * po/fr.po: Updated French translation.
binutils* po/fr.po: Updated French translation.
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gas/
* testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop.
* testsuite/gas/riscv/c-zero-imm.d: Likewise.
opcodes/
* riscv-opc.c (match_c_nop): New.
(riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
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bfd/
* version.m4: Bump version to 2.30.51
* configure: Regenerate.
binutils/
* configure: Regenerate.
gas/
* configure: Regenerate.
gprof/
* configure: Regenerate.
ld/
* configure: Regenerate.
opcodes/
* configure: Regenerate.
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AVX512_4FMAPS and AVX512_4VNNIW insns are marked as having AVX512VL
variants. That is wrong as SDM doesn't define such instructions. The
patch removes these VL variants.
gas/
* testsuite/gas/i386/avx512_4fmaps-warn.l: Change xmm to zmm.
* testsuite/gas/i386/avx512_4fmaps-warn.s: Likewise.
* testsuite/gas/i386/avx512_4fmaps_vl-intel.d: Delete.
* testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Likewise.
* testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Likewise.
* testsuite/gas/i386/avx512_4fmaps_vl.d: Likewise.
* testsuite/gas/i386/avx512_4fmaps_vl.s: Likewise.
* testsuite/gas/i386/avx512_4vnniw_vl-intel.d: Likewise.
* testsuite/gas/i386/avx512_4vnniw_vl.d: Likewise.
* testsuite/gas/i386/avx512_4vnniw_vl.s: Likewise.
* testsuite/gas/i386/i386.exp: Delete _vl tests for 4fmaps an
4vnniw tests.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Delete.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s: Likewise.
opcodes/
* i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW
insns.
* i386-tbl.h: Regenerate.
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Just like their packed counterparts the memory operand is always 16
bytes wide, and the Disp8 scaling is the same for all of them. (As a
side note: I'm also surprised by there being AVX512VL variants of
these as well as the AVX512_4VNNIW ones - the SDM doesn't define any
such.)
Adjust the test cases also for the packed forms to actually live up to
their promise of testing correct Disp8 encoding.
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In commit 2645e1d079 ("x86: add support for AVX-512 VPCMP*{B,W}
pseudo-ops") I screwed up the Disp8MemShift values of the AVX512VL
variants.
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gas/
* testsuite/gas/riscv/auipc-x0.d: New.
* testsuite/gas/riscv/auipc-x0.s: New.
opcodes/
* riscv-dis.c (maybe_print_address): If base_reg is zero,
then the hi_addr value is zero.
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CSDB is a new instruction which Arm has defined. As it shares the
encoding space with NOP instructions, it is available from Armv3 in
Arm mode, and Armv6T2 in Thumb mode.
OK? If so, please commit on my behalf as I don't have commit rights
over here.
Thanks, James
---
opcodes/
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* arm-dis.c (arm_opcodes): Add csdb.
(thumb32_opcodes): Add csdb.
gas/
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (insns): Add csdb, enable for Armv3 and above
in Arm execution state, and Armv6T2 and above in Thumb execution
state.
* testsuite/gas/arm/csdb.s: New.
* testsuite/gas/arm/csdb.d: New.
* testsuite/gas/arm/thumb2_it_bad.l: Add csdb.
* testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
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CSDB is a new instruction which Arm has defined. It has the same encoding as
HINT #0x14 and is available at all architecture levels.
opcodes * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas * testsuite/gas/aarch64/system.d: Update expected results to expect
CSDB.
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For historical reason, we allow movd/vmovd with 64-bit register and
memeory operands. But for vmovd, we failed to handle 64-bit memeory
operand. This has been gone unnoticed since AT&T syntax always treats
memory operand as 32-bit memory. This patch properly encodes vmovd
with 64-bit memeory operands. It also removes AVX512 vmovd with 64-bit
operands since GCC has
case TYPE_SSEMOV:
switch (get_attr_mode (insn))
{
case MODE_DI:
/* Handle broken assemblers that require movd instead of movq. */
if (!HAVE_AS_IX86_INTERUNIT_MOVQ
&& (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
return "%vmovd\t{%1, %0|%0, %1}";
return "%vmovq\t{%1, %0|%0, %1}";
and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't
generate AVX512 vmovd with 64-bit operand.
gas/
PR gas/22681
* testsuite/gas/i386/i386.exp: Run x86-64-movd and
x86-64-movd-intel.
* testsuite/gas/i386/x86-64-movd-intel.d: New file.
* testsuite/gas/i386/x86-64-movd.d: Likewise.
* testsuite/gas/i386/x86-64-movd.s: Likewise.
opcodes/
PR gas/22681
* i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
Remove AVX512 vmovd with 64-bit operands.
* i386-tbl.h: Regenerated.
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ld/
* testsuite/ld-riscv-elf/disas-jalr.d: New.
* testsuite/ld-riscv-elf/disas-jalr.s: New.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run new testcase.
opcodes/
* riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
jalr.
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Other than the variables in tc-i386.c using them, OPERAND_TYPE_REGYMM
and OPERAND_TYPE_REGZMM they aren't entirely unused. No need to update
i386-init.h though, as it mistakenly wasn't updated by the original
commit.
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gas/
* config/tc-riscv.c (risc_ip) <o>: Add comment.
* testsuite/gas/riscv/c-nonzero-imm.d,
* testsuite/gas/riscv/c-nonzero-imm.l,
* testsuite/gas/riscv/c-nonzero-imm.s,
* testsuite/gas/riscv/c-nonzero-reg.d,
* testsuite/gas/riscv/c-nonzero-reg.l,
* testsuite/gas/riscv/c-nonzero-reg.s,
* testsuite/gas/riscv/c-zero-imm-64.d,
* testsuite/gas/riscv/c-zero-imm-64.s,
* testsuite/gas/riscv/c-zero-imm.d, testsuite/gas/riscv/c-zero-imm.s,
* testsuite/gas/riscv/c-zero-reg.d,
* testsuite/gas/riscv/c-zero-reg.s: New.
opcodes/
* riscv-opc.c (match_c_add_with_hint, match_c_lui_with_hint): New.
(riscv_opcodes) <li>: Delete "d,0" line. Change Cj to Co.
<andi, and, add, addiw, addw, c.addi>: Change Cj to Co.
<add>: Add explanatory comment for 4-operand add instruction.
<c.nop>: Add support for immediate operand.
<c.mv, c.add>: Use match_c_add_with_hint instead of match_c_add.
<c.lui>: Use match_c_lui_with_hint instead of match_c_lui.
<c.li, c.slli>: Use match_opcode instead of match_rd_nonzero.
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Dot products deviate from the normal disassembly rules for lane indexed
instruction. Their canonical representation is in the form of:
v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote
that these instructions select 4x 1 byte elements instead of a single 1 byte
element.
Previously we were disassembling them following the normal rules, this patch
corrects the disassembly.
gas/
PR gas/22559
* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B.
* gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly.
include/
PR gas/22559
* aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B.
opcodes/
PR gas/22559
* aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
AARCH64_OPND_QLF_S_4B
* aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
AARCH64_OPND_QLF_S_4B
* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
* aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
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Previously parse_vector_type_for_operand was changed to allow the use of 4b
register size for indexed lane instructions. However this had the unintended
side effect of also allowing 4b for normal vector registers.
Because this support was only partial the rest of the tool silently treated
4b as 8b and continued. This patch adds full support for 4b so it can be
properly distinguished from 8b and the correct errors are generated.
With this patch you still can't encode any instruction which actually requires
v<num>.4b but such instructions don't exist so to prevent needing a workaround
in get_vreg_qualifier_from_value this was just omitted.
gas/
PR gas/22529
* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_V_4B.
* gas/testsuite/gas/aarch64/pr22529.s: New.
* gas/testsuite/gas/aarch64/pr22529.d: New.
* gas/testsuite/gas/aarch64/pr22529.l: New.
include/
PR gas/22529
* opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B.
opcodes/
PR gas/22529
* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
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Just like for instructions in GPRs, there's no need to have separate
templates for otherwise identical insns acting on XMM or YMM registers
(or memory of the same size).
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... qualified by their respective sizes, allowing to drop FirstXmm0 at
the same time.
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Express them as Reg|Tbyte and Acc|Tbyte respectively.
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Use a combination of a single new Reg bit and Byte, Word, Dword, or
Qword instead.
Besides shrinking the number of operand type bits this has the benefit
of making register handling more similar to accumulator handling (a
generic flag is being accompanied by a "size qualifier"). It requires,
however, to split a few insn templates, as it is no longer correct to
have combinations like Reg32|Reg64|Byte. This slight growth in size will
hopefully be outweighed by this change paving the road for folding a
presumably much larger number of templates later on.
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* disassemble.c (disassemble_init_for_target): Don't put PRU
between powerpc and rs6000 cases.
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|
They are relevant only when multiple operands permit registers:
operand_type_register_match() returns true if either operand is not a
register one. IOW
grep -i CheckRegSize i386-opc.tbl | grep -Ev "(Reg[8136]|Acc).*,.*(Reg|Acc)"
should produce no output.
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PR 22599
gas/
* testsuite/gas/riscv/fsxxi.d, testsuite/gas/riscv/fsxxi.s: New.
opcodes/
* riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
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correct symbols when disassembling arguments of "call" instructions with a relocation.
opcodes * disassemble.c: Enable disassembler_needs_relocs for PRU.
gas * testsuite/gas/pru/extern.s: New test for print of U16_PMEMM
relocation.
* testsuite/gas/pru/extern.d: New test driver.
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symbol backward.
When checking mapping symbols backwardly, the section which defines the symbol
is not considerted. This patch fixes this by moving the section checking code
into get_sym_code_type () function which is shared by forward and backword
mapping symbol searching.
opcodes/
2017-12-11 Petr Pavlu <petr.pavlu@arm.com>
Renlin Li <renlin.li@arm.com>
* aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
(get_sym_code_type): Here.
binutils/
2017-12-11 Renlin Li <renlin.li@arm.com>
* testsuite/binutils-all/aarch64/objdump.d: New.
* testsuite/binutils-all/aarch64/objdump.s: New.
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Correct sign extension.
* ppc-opc.c (extract_li20): Rewrite.
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|
include/
* opcode/ppc.h (PPC_INT_FMT): Define.
(struct powerpc_opcode) <opcode>: Update type.
(struct powerpc_opcode) <mask>: Likewise.
(struct powerpc_opcode) <bitm>: Likewise.
(struct powerpc_opcode) <insert>: Likewise.
(struct powerpc_opcode) <extract>: Likewise.
(ppc_optional_operand_value): Likewise.
gas/
* config/tc-ppc.c (last_insn): Update type.
(insn_validate) <omask, mask>: Likewise.
(ppc_setup_opcodes) <mask, right_bit>: Likewise.
<PRINT_OPCODE_TABLE>: Update types and printf format specifiers.
(ppc_insert_operand): Update return and argument types and remove
unneeded type casts.
<min, max, right, tmp>: Update type.
(md_assemble): Remove unneeded type casts.
<insn, val, tmp_insn>: Update type.
opcodes/
* opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
(operand_value_powerpc): Update return and argument type.
<value, top>: Update type.
(skip_optional_operands): Update argument type.
(lookup_powerpc): Likewise.
(lookup_vle): Likewise.
<table_opcd, table_mask, insn2>: Update type.
(lookup_spe2): Update argument type.
<table_opcd, table_mask, insn2>: Update type.
(print_insn_powerpc) <insn, value>: Update type.
Use PPC_INT_FMT for printing instructions and operands.
* opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
(OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
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|
BaseIndex implies - with the exception of string instructions the
optional presence of a displacement. This is almost completely uniform
for all instructions (the sole exception being MPX ones, which don't
allow 16-bit addressing and hence Disp16), so there's no point in
explicitly stating this in the main opcode table. Drop those explict
specifications in favor of adding logic to i386-gen, shrinking the
table size quite a bit and hence making it more readable.
The opcodes/i386-tbl.h changes are due to a few cases where pointless
Disp* still hadn't been removed from their insns.
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This is fully redundant with Disp8MemShift being non-zero, and hence can
be folded with normal Disp8 handling.
|
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bfd/
* po/Make-in (datadir): Define as @datadir@.
(localedir): Define as @localedir@.
(gnulocaledir, gettextsrcdir): Use @datarootdir@.
binutils/
* po/Make-in (datadir): Define as @datadir@.
(localedir): Define as @localedir@.
(gnulocaledir, gettextsrcdir): Use @datarootdir@.
gas/
* po/Make-in (datadir): Define as @datadir@.
(localedir): Define as @localedir@.
(gnulocaledir, gettextsrcdir): Use @datarootdir@.
gold/
* po/Make-in (datadir): Define as @datadir@.
(localedir): Define as @localedir@.
(gnulocaledir, gettextsrcdir): Use @datarootdir@.
gprof/
* po/Make-in (datadir): Define as @datadir@.
(localedir): Define as @localedir@.
(gnulocaledir, gettextsrcdir): Use @datarootdir@.
ld/
* po/Make-in (datadir): Define as @datadir@.
(localedir): Define as @localedir@.
(gnulocaledir, gettextsrcdir): Use @datarootdir@.
opcodes/
* po/Make-in (datadir): Define as @datadir@.
(localedir): Define as @localedir@.
(gnulocaledir, gettextsrcdir): Use @datarootdir@.
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library.
* po/zh_CN.po: Updated simplified Chinese translation.
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|
"fi*" typically come in two (loads/stores: three) flavors, distinguished
by the suffix. Don't omit the 's' one when disassembling.
|
|
opcodes/
* i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
* i386-tbl.h: Regenerate.
gas/
* testsuite/gas/i386/avx512f_vaes-intel.d: Regenerate.
* testsuite/gas/i386/avx512f_vaes.d: Likewise.
* testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Likewise.
* testsuite/gas/i386/avx512f_vaes-wig1.d: Likewise.
* testsuite/gas/i386/avx512vl_vaes-intel.d: Likewise.
* testsuite/gas/i386/avx512vl_vaes.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_vaes.s: Add instructions with disp8*N.
* testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Regenerate.
* testsuite/gas/i386/x86-64-avx512f_vaes.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Add instructions with disp8*N.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Regenerate.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Regenerate.
* testsuite/gas/i386/x86-64-avx512vl_vaes.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Add instructions with disp8*N.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Regenerate.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Regenerate.
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|
Despite EVEX encodings not being available in real and VM86 modes,
16-bit addressing still needs to be handled properly for 16-bit
protected mode as well as 16-bit addressing in 32-bit mode. Neither
should displacements be dropped silently by the assembler, nor should
the disassembler fail to correctly scale 8-bit displacements.
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Make the assembler recognize UD0, supporting only the newer form
expecting a ModR/M byte.
Make assembler and disassembler properly emit / expect a ModR/M byte for
UD1.
For the testsuite, as arch-4 already tests all UDn, avoid producing a
huge delta for other tests using UD2B by making them use UD2 instead.
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* i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
* i386-tbl.h: Regenerate.
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