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2017-11-22Remove Vec_Disp8 from vpcompressb and vpexpandb.Igor Tsimbalist2-13/+12
2017-11-22[ARC] Fix handling of ARCv2 H-register class.claziss2-0/+6
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss3-17/+52
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina2-2/+7
2017-11-16Correct AArch64 crypto dependencies.Tamar Christina1-4/+6
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina3-2925/+3534
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich2-28/+47
2017-11-15x86: use correct register namesJan Beulich2-3/+8
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich2-50/+45
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich3-2/+7
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich2-8/+67
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich4-29/+1554
2017-11-14x86: string insns don't allow displacementsJan Beulich3-42/+48
2017-11-13x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffixJan Beulich3-10/+16
2017-11-09Add assembler and disassembler support for the new Armv8.4-a registers for AA...Tamar Christina2-1/+164
2017-11-09Add the operand encoding types for the new Armv8.2-a back-ported instructions...Tamar Christina2-0/+97
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina11-179/+296
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina2-0/+37
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton2-17/+39
2017-11-08Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang2-0/+24
2017-11-07opcodes/arc: Fix incorrect insn_class for some nps insnsAndrew Burgess2-4/+8
2017-11-07ngettext supportAlan Modra2-16/+35
2017-11-03[ARC] Force the disassam to use the hexadecimal number for printingclaziss2-1/+21
2017-11-03[ARC] Sync opcode data base.claziss3-1588/+3455
2017-10-25PR22348, conflicting global vars in crx and cr16Alan Modra4-20/+33
2017-10-24RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman2-7/+33
2017-10-23Add missing ChangeLog entriesIgor Tsimbalist1-0/+110
2017-10-23Fix the master due to bad regenerated filesIgor Tsimbalist3-5469/+11545
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist5-3/+51
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist5-6/+48
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist5-14/+30
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist7-5576/+5902
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist7-5443/+6011
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist7-5389/+6652
2017-10-18[Visium] Disassemble the operands of the stop instruction.Eric Botcazou2-1/+5
2017-10-12FT32: support for FT32B processor - part 1James Bowman3-22/+49
2017-10-09S/390: Sync with latest POP - 3 new instructionsAndreas Krebbel2-0/+8
2017-10-09S/390: Sync with IBM z14 POP - SI_RD formatAndreas Krebbel3-4/+13
2017-10-01Add new mnemonics for VLE multiple load instructionsAlexander Fedotov2-0/+15
2017-09-27Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...Nick Clifton2-0/+11
2017-09-26Allow the macw and macl instructions to be used on CPUs that have emacs support.Nick Clifton2-0/+20
2017-09-25Initialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm (and fix breakage on ...Sergio Durigan Junior2-1/+5
2017-09-11nds32: Rename __BIT() to N32_BIT().Kuan-Lin Chen4-40/+46
2017-09-09x86: Remove restriction on NOTRACK prefix positionH.J. Lu2-16/+8
2017-08-31Add updated French translations for opcodes and gprofNick Clifton2-418/+786
2017-08-30FT32: improve disassembly readabilityJames Bowman2-7/+17
2017-08-24[PowerPC VLE] Add SPE2 and EFS2 instructions supportAlexander Fedotov3-12/+1239
2017-08-23ppc-opc.c formattingAlan Modra2-1089/+1101
2017-08-22RISC-V: Mark "c.nop" as an aliasPalmer Dabbelt2-1/+5
2017-08-21[PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction supportAlexander Fedotov3-6/+920
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