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2021-08-04IBM Z: Remove lpswey parameterAndreas Krebbel2-1/+3
opcodes/ * s390-opc.c (INSTR_SIY_RD): New instruction format. (MASK_SIY_RD): New instruction mask. * s390-opc.txt: Change instruction format of lpswey to SIY_RD. gas/ * testsuite/gas/s390/zarch-arch14.d: Remove last operand of lpswey. * testsuite/gas/s390/zarch-arch14.s: Likewise.
2021-07-27Correct gs264e bfd_mach in mips_arch_choices.Chenghua Xu2-1/+5
opcodes/ * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
2021-07-26PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_pacg'. (do_t_pacbti_pacg): New function. (insns): Define 'pacg' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacg' test. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'pacg'.
2021-07-26PATCH [8/10] arm: add 'autg' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_autg'. (insns): Define 'autg' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add autg test. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'autg'.
2021-07-26PATCH [7/10] arm: add 'bxaut' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_bxaut'. (do_t_pacbti_nonop): New function. (insns): Define 'bxaut' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'bxaut' test. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'bxaut'.
2021-07-26PATCH [4/10] arm: add 'pac' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (T16_32_TAB): Add '_pac'. (insns): Add 'pac' insn. * testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Add pac tests. * testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.d: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'pac'.
2021-07-26PATCH [3/10] arm: add 'aut' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (insns): Add 'aut.' (T16_32_TAB): Add '_aut'. * testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Add 'aut' tests. * testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.d: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'aut'.
2021-07-26PATCH [2/10] arm: add 'pacbti' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (enum operand_parse_code): Add OP_SP and OP_R12. (parse_operands): Add switch cases for OP_SP and OP_R12. (T16_32_TAB): Add '_pacbti'. (do_t_pacbti): New function. (insns): Add 'pacbti'. * testsuite/gas/arm/armv8_1-m-pacbti-bad.d: New file. * testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise. * testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacbti' to testcase. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add 'pacbti' instruction.
2021-07-26PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+5
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (insns): Add 'bti' insn. * testsuite/gas/arm/armv8_1-m-pacbti.d: New file. * testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise. opcodes/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * arm-dis.c (thumb32_opcodes): Add bti instruction.
2021-07-23x86: express unduly set rounding control bits in disassemblyJan Beulich1-37/+53
While EVEX.L'L are indeed ignored when EVEX.b stands for just SAE, EVEX.b itself is not ignored when an insn permits neither rounding control nor SAE. While changing this aspect of EVEX.b handling, also alter unduly set embedded broadcast: Don't call BadOp(), screwing up subsequent disassembly, but emit "{bad}" instead.
2021-07-22x86: drop dq{b,d}_modeJan Beulich1-30/+13
Their sole use is for {,V}EXTRACTPS / {,V}P{EXT,INS}RB respectively; for consistency also limit use of dqw_mode to Jdqw. 64-bit disassembly reflecting REX.W / VEX.W is not in line with the assembler's opcode table having NoRex64 / VexWIG in all respective templates, i.e. assembly input isn't being honored there either. Obviously the 0FC5 encodings of {,V}PEXTRW then also need adjustment for consistency reasons.
2021-07-22x86: drop vex_scalar_w_dq_modeJan Beulich3-51/+41
It has only a single use and can easily be represented by dq_mode instead. Plus its handling in intel_operand_size() was duplicating that of vex_vsib_{d,q}_w_dq_mode anyway.
2021-07-22x86: drop xmm_m{b,w,d,q}_modeJan Beulich4-164/+91
They're effectively redundant with {b,w,d,q}_mode.
2021-07-22x86: fold duplicate vector register printing codeJan Beulich1-74/+33
The bulk of OP_XMM() can be easily reused also for OP_EX(). Break the shared logic out of the function, and invoke the new helper from both places.
2021-07-22x86: drop vex_mode and vex_scalar_modeJan Beulich1-11/+7
These are fully redundant with, respectively, x_mode and scalar_mode.
2021-07-22x86: correct EVEX.V' handling outside of 64-bit modeJan Beulich1-4/+16
Unlike the high bit of VEX.vvvv / EVEX.vvvv, EVEX.V' is not ignored outside of 64-bit mode. Oddly enough there already are tests for these cases, but their expectations were wrong. (This may have been based on an old SDM version, where the restriction wasn't properly spelled out.)
2021-07-22x86: fold duplicate code in MOVSXD_Fixup()Jan Beulich1-16/+10
There's no need to have two paths printing the "xd" mnemonic suffix.
2021-07-22x86: fold duplicate register printing codeJan Beulich1-105/+14
What so far was OP_E_register() can be easily reused also for OP_G(). Add suitable parameters to the function and move the invocation of swap_operand() to OP_E(). Adjust MOVSXD's first operand: There never was a need to use movsxd_mode there, and its use gets in the way of the code folding.
2021-07-22x86-64: properly bounds-check %bnd<N> in OP_G()Jan Beulich1-1/+1
The restriction to %bnd0-%bnd3 requires to also check REX.R is clear, just like OP_E_Register() also includes REX.B in its check.
2021-07-22x86-64: generalize OP_G()'s EVEX.R' handlingJan Beulich1-1/+8
EVEX.R' is invalid to be clear not only for mask registers, but also for GPRs - IOW everything handled in this function.
2021-07-22x86: correct VCVT{,U}SI2SD rounding mode handlingJan Beulich3-15/+3
With EVEX.W clear the instruction doesn't ignore the rounding mode, but (like for other insns without rounding semantics) EVEX.b set causes #UD. Hence the handling of EVEX.W needs to be done when processing evex_rounding_64_mode, not at the decode stages. Derive a new 64-bit testcase from the 32-bit one to cover the different EVEX.W treatment in both cases.
2021-07-22x86: drop OP_Mask()Jan Beulich4-48/+28
By moving its vex.r check there it becomes fully redundant with OP_G().
2021-07-14x86: Add int1 as one byte opcode 0xf1H.J. Lu3-1/+15
Also change the x86 disassembler to disassemble 0xf1 as int1, instead of icebp. gas/ PR gas/28088 * testsuite/gas/i386/opcode.s: Add int1. * testsuite/gas/i386/x86-64-opcode.s: Add int1, int3 and int. * testsuite/gas/i386/opcode-intel.d: Updated. * testsuite/gas/i386/opcode-suffix.d: Likewise. * testsuite/gas/i386/opcode.d: Likewise. * testsuite/gas/i386/x86-64-opcode.d: Likewise. opcodes/ PR gas/28088 * i386-dis.c (dis386): Replace icebp with int1. * i386-opc.tbl: Add int1. * i386-tbl.h: Regenerate.
2021-07-07Add changelog entries for last commitAndreas Krebbel1-0/+4
2021-07-07IBM Z: Add another arch14 instructionAndreas Krebbel1-0/+2
opcodes/ * opcodes/s390-opc.txt: Add qpaci. gas/ * testsuite/gas/s390/zarch-arch14.d: Add qpaci. * testsuite/gas/s390/zarch-arch14.s: Add qpaci.
2021-07-05Updated translations (mainly Ukranian and French) triggered by creation of ↵Nick Clifton3-709/+868
2.37 branch.
2021-07-03Update version number and regenerate filesNick Clifton3-220/+254
2021-07-03Add markers for 2.37 branchNick Clifton1-0/+4
2021-07-02Re: Fix minor NDS32 renaming snafuAlan Modra3-12/+21
Some extern declarations differ in constnes to their definitions too. Let's make sure this sort of thing doesn't happen again, but putting the externs in a header where they belong. gas/ * config/tc-nds32.c (nds32_keyword_gpr): Don't declare. (md_begin): Constify k. opcodes/ * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return. (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg. (nds32_field_table, nds32_opcode_table, nds32_keyword_table), (nds32_opcodes, nds32_operand_fields, nds32_keywords), (nds32_keyword_gpr): Move declarations to.. * nds32-asm.h: ..here, constifying to match definitions.
2021-07-01cgen: split GUILE setting outMike Frysinger3-2/+10
This makes it easier to override to point to an older version of guile. The current cgen code doesn't work with guile-2, so need to point to an older guile-1.8.
2021-07-01opcodes: constify & local meps macrosMike Frysinger2-5/+12
Avoid exporting this common variable name into writable data.
2021-07-01opcodes: cleanup nds32 variablesMike Frysinger3-40/+57
For the variables that don't need to be exported, mark them static. For the ones shared between modules, add a "nds32_" prefix to avoid collisions with these common variable names.
2021-07-01opcodes: constify & localize z80 opcodesMike Frysinger2-2/+7
These aren't used outside of this module, and are never modified. Mark it static to avoid bad exported variable name issues.
2021-07-01opcodes: constify & scope microblaze opcodesMike Frysinger3-11/+23
This is exporting the variable "opcodes" as a large writable blob. This is not a namespace friendly name, so add a "microblaze" prefix, and then sprinkle const over its definition & use.
2021-07-01opcodes: constify aarch64_opcode_tablesMike Frysinger3-3/+8
This table is huge (~350k), so stop putting it into writable .data since it's only const data.
2021-06-22opcodes: make use of __builtin_popcount when availableAndrew Burgess2-0/+9
This commit provides a small performance improvement when starting up CGEN based disassemblers by making use of __builtin_popcount. The #if check used in this commit was copied from bfd/elf32-arm.c where __builtin_popcount is also used. I ran into this code while investigating some GDB tests that would occasionally timeout. One of the reason these tests were having problems is that the m16c and m32c disassemblers take so long to initialise themselves. Speeding up count_decodable_bits helps, but is not a total solution. Still, this felt like an easy win which added minimal extra complexity, so I figure its worth doing. opcodes/ChangeLog: * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when available.
2021-06-22picojava assembler and disassembler fixesAlan Modra2-2/+8
Commit 54758c3e398d made changes to the picojava support based on https://sourceware.org/pipermail/binutils/2005-November/045136.html An update from picojava to picojava II, I think. Unfortunately the patch neglected any changes to the gas testsuite, resulting in "FAIL: pj" since that date. This patch makes a few relatively simple changes to cure the regression. gas/ * config/tc-pj.c (md_apply_fix): Apply PJ_CODE_REL32 relocs. * testsuite/gas/pj/ops.s: Update jsr, ret, getstatic, putstatic, getfield, putfield, invokevirtual, invokespecial, invokestatic, invokeinterface, goto_w, jsr_w assembly. Delete version 1 picojava opcodes. * testsuite/gas/pj/ops.d: Match expected output. opcodes/ * pj-dis.c (print_insn_pj): Don't print trailing tab. Do print separator for pcrel insns.
2021-06-19ubsan: vax: pointer overflowAlan Modra2-1/+5
"VAX export class call relocation test" fails with ubsan on a 32-bit host. * vax-dis.c (print_insn_vax): Avoid pointer overflow.
2021-06-19Fix another strncpy warningAlan Modra2-1/+6
* tic30-dis.c (get_register_operand): Don't ask strncpy to fill entire buffer.
2021-06-17powerpc: move cell "or rx,rx,rx" hintsAlan Modra2-5/+10
* ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location in table.
2021-06-03PR1202, mcore disassembler: wrong address looptAlan Modra2-4/+10
Fixes a 16 year old bug report, which even came with a patch. opcodes/ PR 1202 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly. Use unsigned int for inst. gas/ PR 1202 * testsuite/gas/mcore/allinsn.d: Correct loopt expected output.
2021-06-02arc: Construct disassembler options dynamicallyShahab Vahedi2-27/+161
The idea of this change is simple: Populate a data structure, namely "disasm_option_and_arg_t" from "include/dis-asm.h", to encompass the disassembly options and their possible arguments. This will make it easier to manage or extend those options by adapting entries in a data structure, "arc_options". There will be lesser need to hard-code the options in the code itself. Moreover, ARC GDB will use this population function, "disassembler_options_arc ()", to enable the "set disassembler-option" for ARC targets. The gdb change will be in a separate patch though. The changes in this patch can be divided into: 1) Introduction of "disassembler_options_arc ()" that will return a "disasm_option_and_arg_t" structure representing the disassembly options and their likely arguments. 2) New data type "arc_options_arg_t" and new data "arc_options". These are the internals for keeping track of options and arguments entries that can easily be extended. 3) To print the options, the "print_arc_disassembler_options ()" has been adjusted to use this dynamically built structure instead of having them hard-coded inside. To see this in effect, one can look into the output of: $ ./binutils/objdump --help ... The following ARC specific disassembler options are... ... include/ChangeLog: * dis-asm.h (disassembler_options_arc): New prototype. opcodes/ChangeLog: * arc-dis.c (arc_option_arg_t): New enumeration. (arc_options): New variable. (disassembler_options_arc): New function. (print_arc_disassembler_options): Reimplement in terms of "disassembler_options_arc".
2021-05-29PowerPC table driven -Mraw disassemblyAlan Modra3-1635/+1634
opcodes/ * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many. Don't special case PPC_OPCODE_RAW. (lookup_prefix): Likewise. (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and.. (print_insn_powerpc): ..update caller. * ppc-opc.c (EXT): Define. (powerpc_opcodes): Mark extended mnemonics with EXT. (prefix_opcodes, vle_opcodes): Likewise. (XISEL, XISEL_MASK): Add cr field and simplify. (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort all isel variants to where the base mnemonic belongs. Sort dstt, dststt and dssall. gas/ * testsuite/gas/ppc/raw.s, * testsuite/gas/ppc/raw.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2021-05-29MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructionsMaciej W. Rozycki2-66/+73
Group legacy instructions using the COP0, COP2, COP3 opcodes together and by their coprocessor number, and move them towards the end of the opcode table. No functional change. With the addition of explicit ISA exclusions this is maybe not strictly necessary anymore as the individual legacy instructions are not supposed to match ISA levels or CPU implementations that have discarded them or replaced with a new instruction each, but let's not have them scattered randomly across blocks of unrelated instruction sets where someone chose to put them previously. Perhaps they could be put back in alphabetical order in the main instruction block, but let's leave it for another occasion. opcodes/ * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2, COP3 opcode instructions.
2021-05-29MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki2-51/+61
Adjust opcode table entries for coprocessor instructions that have been removed from certain ISA levels or CPU implementations as follows: - remove CP0 memory access instructions from MIPS II up as the LWC0 and SWC0 opcodes have been reused for the LL and SC instructions respectively[1]; strictly speaking LWC0 and SWC0 have never really been defined in the first place[2], but let's keep them for now in case an odd implementation did, - remove CP0 branch instructions from MIPS IV[3] and MIPS32[4] up, as they have been removed as from those ISAs, - remove CP0 control register move instructions from MIPS32 up, as they have been removed as from that ISA[5], - remove the RFE instruction from MIPS III[6] and MIPS32[7] up, as it has been removed as from those ISAs in favour to ERET, - remove CP2 instructions from Vr5400 CPUs as their encodings have been reused for the multimedia instruction set extensions[8] and no CP2 registers exist[9], - remove CP3 memory access instructions from MIPS III up as coprocessor 3 has been removed as from that ISA[10][11] and from MIPS32 up as the LWC3 opcode has been reused for the PREF instruction and consequently all the four memory access instructions removed from the ISA (though the COP3 opcode has been retained)[12]. Update the testsuite accordingly. References: [1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Table A-38 "CPU Instruction Encoding - MIPS II Architecture", p. A-178 [2] same, Section A.2.5.1 "Coprocessor Load and Store", p. A-12 [3] "MIPS R10000 Microprocessor User's Manual", Version 2.0, MIPS Technologies, Inc., January 29, 1997, Section 14.25 "CP0 Instructions", Subsection "Branch on Coprocessor 0", p. 285 [4] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, June 9, 2003, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [5] same [6] Joe Heinrich, "MIPS R4000 Microprocessor User's Manual", Second Edition, MIPS Technologies, Inc., April 1, 1994, Figure A-2 "R4000 Opcode Bit Encoding", p. A-182 [8] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 1", NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000, Section 1.2.3 "CPU Instruction Set Overview", p. 9 [9] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 2", NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000, Section 19.2 "Multimedia Instruction Format", p. 681 [10] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3 and CP3 load/store", p. A-176 [11] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture", p. A-179 [12] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-2 "MIPS32 Encoding of the Opcode Field", p. 241 opcodes/ * mips-opc.c (mips_builtin_opcodes): Update exclusion list for "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0", "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t", "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2", "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3", "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3", "cop2", and "cop3" entries. gas/ * testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3 instruction removal. * testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.
2021-05-29MIPS/opcodes: Remove DMFC3 and DMTC3 instructionsMaciej W. Rozycki2-4/+5
Coprocessor 3 has been removed from the MIPS ISA as from MIPS III[1][2] with the LDC3 and SDC3 instructions having been replaced with LD and SD instructions respectively and therefore the doubleword move instructions from and to that coprocessor have never materialized (for 32-bit ISAs coprocessor 3 has likewise been removed as from MIPS32r2[3]). Remove the DMFC3 and DMTC3 instructions from the opcode table then to avoid confusion. References: [1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3 and CP3 load/store", p. A-176 [2] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture", p. A-179 [3] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 2.00, June 9, 2003, Table A-2 "MIPS32 Encoding of the Opcode Field", p. 317 opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3" entries and associated comments.
2021-05-29MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki2-2/+8
Fix a commit b015e599c772 ("[MIPS] Add new virtualization instructions"), <https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression and bring the disassembly of the RFE instruction back for the relevant ISA levels. It is because the "rfe" opcode table entry was incorrectly moved behind the catch-all generic "c0" entry for CP0 instructions, causing output like: 00: 42000010 c0 0x10 to be produced rather than: 00: 42000010 rfe even for ISA levels that do include the RFE instruction. Move the "rfe" entry ahead of "c0" then, correcting the problem. Add a suitable test case. opcodes/ * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead of "c0". gas/ * testsuite/gas/mips/rfe.d: New test. * testsuite/gas/mips/rfe.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2021-05-29MIPS/opcodes: Add legacy CP1 control register namesMaciej W. Rozycki2-25/+47
The two CP1 control registers defined by legacy ISAs used to be referred to by various names, such as FCR0, FCR31, FSR, however their documented full names have always been the Implementation and Revision, and Control and Status respectively, so the FIR and FCSR acronyms coming from modern ISA revisions will be just as unambiguous while improving the clarity of disassembly. Do not update the TX39 though as it did not have an FPU. opcodes/ * mips-dis.c (mips_cp1_names_mips): New variable. (mips_arch_choices): Use it rather than `mips_cp1_names_numeric' for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120", "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500", "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000", "r12000", "r14000", "r16000", "mips5", "loongson2e", and "loongson2f". gas/ * testsuite/gas/mips/cp1-names-r3900.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. * testsuite/gas/mips/branch-misc-3.d: Update disassembly according to changes to opcodes. * testsuite/gas/mips/cp1-names-r3000.d: Likewise. * testsuite/gas/mips/cp1-names-r4000.d: Likewise. * testsuite/gas/mips/relax-swap1-mips1.d: Likewise. * testsuite/gas/mips/relax-swap1-mips2.d: Likewise. * testsuite/gas/mips/trunc.d: Likewise.
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki4-17/+39
The CP0 control register set has never been defined, however encodings for the CFC0 and CTC0 instructions remained available for implementers up until the MIPS32 ISA declared them invalid and causing the Reserved Instruction exception[1]. Therefore we handle them for both assembly and disassembly, however in the latter case the names of CP0 registers from the regular set are incorrectly printed if named registers are requested. This is because we do not define separate operand classes for coprocessor regular and control registers respectively, which means the disassembler has no way to tell the two cases apart. Consequently nonsensical disassembly is produced like: cfc0 v0,c0_random Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0 instructions[2] although it failed to document them in the relevant opcode table until MIPSr6 only. Correct the issue then by defining a new register class, OP_REG_CONTROL, and corresponding operand codes, `g' and `y' for the two positions in the machine instruction a control register operand can take. Adjust the test cases affected accordingly. While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries with each other so that they come in the alphabetical order. References: [1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 195, 216 include/ * opcode/mips.h: Document `g' and `y' operand codes. (mips_reg_operand_type): Add OP_REG_CONTROL enumeration constant. gas/ * tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case. (macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G' operand code. opcodes/ * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register handling code over to... <OP_REG_CONTROL>: ... this new case. * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries replacing the `G' operand code with `g'. Update "cftc1" and "cftc2" entries replacing the `E' operand code with `y'. * micromips-opc.c (decode_micromips_operand) <'g'>: New case. (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" entries replacing the `G' operand code with `g'. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0 operand disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
2021-05-29MIPS/opcodes: Add TX39 CP0 register namesMaciej W. Rozycki2-1/+19
The TX39 core has its distinct set of CP0 registers[1], so it needs a separate table to hold their names. Add a test case accordingly. References: [1] "32-Bit RISC Microprocessor TX39 Family Core Architecture User's Manual", Toshiba, Jul. 27, 1995, Section 2.2.2 "System control coprocessor (CP0) registers", pp. 9-10 opcodes/ * mips-dis.c (mips_cp0_names_r3900): New variable. (mips_arch_choices): Use it rather than `mips_cp0_names_numeric' for "r3900". gas/ * testsuite/gas/mips/cp0-names-r3900.d: New test. * testsuite/gas/mips/mips.exp: Run it.
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