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2018-09-23Fix incorrect extraction of signed constants in nios2 disassembler.Sandra Loosemore2-13/+21
2018-09-23 Sandra Loosemore <sandra@codesourcery.com> opcodes/ * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions are used when extracting signed fields and converting them to potentially 64-bit types.
2018-09-21csky-opc.h: Initialize fields of last array elementsSimon Marchi7-68/+14
clang gives these errors: In file included from /Users/simark/src/binutils-gdb/opcodes/csky-dis.c:30: /Users/simark/src/binutils-gdb/opcodes/csky-opc.h:2330:8: error: missing field 'transfer' initializer [-Werror,-Wmissing-field-initializers] {NULL} ^ /Users/simark/src/binutils-gdb/opcodes/csky-opc.h:8126:10: error: missing field 'transfer' initializer [-Werror,-Wmissing-field-initializers] {NULL} ^ They go away when we Initialize all fields. I noticed there used to be some files built with -Wno-missing-field-initializers, but it's not the case anymore, since commit e7ae278d0474ab84ba3b1ee932a19e83616ddacc. There is still a NO_WMISSING_FIELD_INITIALIZERS variable defined in the Makefile, but it's unused, so I removed it to avoid further confusion. opcodes/ChangeLog: * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS. * Makefile.in: Re-generate. * aclocal.m4: Re-generate. * configure: Re-generate. * configure.ac: Remove check for -Wno-missing-field-initializers. * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element. (csky_v2_opcodes): Likewise.
2018-09-20ARC: Fix build errors with large constants and C89Maciej W. Rozycki2-26/+30
Fix build errors: cc1: warnings being treated as errors In file included from .../opcodes/arc-opc.c:2630: .../opcodes/arc-nps400-tbl.h:38: warning: integer constant is too large for 'long' type .../opcodes/arc-nps400-tbl.h:38: warning: integer constant is too large for 'long' type .../opcodes/arc-nps400-tbl.h:41: warning: integer constant is too large for 'long' type .../opcodes/arc-nps400-tbl.h:41: warning: integer constant is too large for 'long' type [...] .../opcodes/arc-nps400-tbl.h:712: warning: integer constant is too large for 'long' type .../opcodes/arc-nps400-tbl.h:712: warning: integer constant is too large for 'long' type .../opcodes/arc-nps400-tbl.h:715: warning: integer constant is too large for 'long' type .../opcodes/arc-nps400-tbl.h:715: warning: integer constant is too large for 'long' type make[4]: *** [arc-opc.lo] Error 1 and: cc1: warnings being treated as errors .../gas/config/tc-arc.c: In function 'md_number_to_chars_midend': .../gas/config/tc-arc.c:802: warning: integer constant is too large for 'long' type .../gas/config/tc-arc.c:810: warning: integer constant is too large for 'long' type make[4]: *** [config/tc-arc.o] Error 1 observed with GCC 4.1.2 and presumably other C89 compilers with the `arc-elf' and `arc-linux-gnu' targets, caused by the use of constants the values of which are outside the range of the `int' type (or the `long' type if it is of the same with). In the C89 language standard such constants are not implicitly converted to a wider type and an explicit suffix is required for such constants. Add a `ull' suffix then as with such constants used in other ports. gas/ * config/tc-arc.c (md_number_to_chars_midend): Append `ull' to large constants. opcodes/ * arc-nps400-tbl.h: Append `ull' to large constants throughout.
2018-09-20Andes Technology has good news for you, we plan to update the nds32 port of ↵Nick Clifton5-300/+944
binutils on upstream! We have not only removed all unsupported and obsolete code, but also supported lost of new features, including better link-time relaxations and TLS implementations. Besides, the files generated by the newly assembler and linker usually get higher performance and more optimized code size. ld * emultempl/nds32elf.em (hyper_relax): New variable. (nds32_elf_create_output_section_statements): the parameters of bfd_elf32_nds32_set_target_option (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Add new option --mhyper-relax. * emultempl/nds32elf.em (nds32_elf_after_open): Updated. * emultempl/nds32elf.em (tls_desc_trampoline): New variable. * (nds32_elf_create_output_section_statements): Updated. * (nds32_elf_after_parse): Disable relaxations when PIC is enable. * (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Add new option --m[no-]tlsdesc-trampoline. include * elf/nds32.h: Remove the unused target features. * dis-asm.h (disassemble_init_nds32): Declared. * elf/nds32.h (E_NDS32_NULL): Removed. (E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New. * opcode/nds32.h: Ident. (N32_SUB6, INSN_LW): New macros. (enum n32_opcodes): Updated. * elf/nds32.h: Doc fixes. * elf/nds32.h: Add R_NDS32_LSI. * elf/nds32.h: Add new relocations for TLS. gas * config/tc-nds32.c: Remove the unused target features. (nds32_relax_relocs, md_pseudo_table, nds32_elf_record_fixup_exp, nds32_set_elf_flags_by_insn, nds32_insert_relax_entry, nds32_apply_fix): Likewise. (nds32_no_ex9_begin): Removed. * config/tc-nds32.c (add_mapping_symbol_for_align, make_mapping_symbol, add_mapping_symbol): New functions. * config/tc-nds32.h (enum mstate): New. (nds32_segment_info_type): Likewise. * configure.ac (--enable-dsp-ext, --enable-zol-ext): New options. * config.in: Regenerated. * configure: Regenerated. * config/tc-nds32.c (nds32_dx_regs): Set the value according to the configuration. (nds32_perf_ext, nds32_perf_ext2, nds32_string_ext, nds32_audio_ext): Likewise. (nds32_dsp_ext): New variable. Set the value according to the configuration. (nds32_zol_ext): Likewise. (asm_desc, nds32_pseudo_opcode_table): Make them static. (nds32_set_elf_flags_by_insn): Updated. (nds32_check_insn_available): Updated. (nds32_str_tolower): New function. * config/tc-nds32.c (relax_table): Updated. (md_begin): Updated. (md_assemble): Use XNEW macro to allocate space for `insn.info', and then remember to free it. (md_section_align): Cast (-1) to ValueT. (nds32_get_align): Cast (~0U) to addressT. (nds32_relax_branch_instructions): Updated. (md_convert_frag): Add new local variable `final_r_type'. (invalid_prev_frag): Add new bfd_boolean parameter `relax'. All callers changed. * config/tc-nds32.c (struct nds32_relocs_pattern): Add `insn' field. (struct nds32_hint_map): Add `option_list' field. (struct suffix_name, suffix_table): Remove the unused `pic' field. (do_pseudo_b, do_pseudo_bal): Remove the suffix checking. (do_pseudo_la_internal, do_pseudo_pushpopm): Indent. (relax_hint_bias, relax_hint_id_current): New static variables. (reset_bias, relax_hint_begin): New variables. (nds_itoa): New function. (CLEAN_REG, GET_OPCODE): New macros. (struct relax_hint_id): New. (nds32_relax_hint): For .relax_hint directive, we can use `begin' and `end' to mark the relax pattern without giving exactly id number. (nds32_elf_append_relax_relocs): Handle the case that the .relax_hint directives are attached to pseudo instruction. (nds32_elf_save_pseudo_pattern): Change the second parameter from instruction's opcode to byte code. (nds32_elf_build_relax_relation): Add new bfd_boolean parameter `pseudo_hint'. (nds32_lookup_pseudo_opcode): Fix the overflow issue. (enum nds32_insn_type): Add N32_RELAX_ALU1 and N32_RELAX_16BIT. (nds32_elf_record_fixup_exp, relax_ls_table, hint_map, nds32_find_reloc_table, nds32_match_hint_insn, nds32_parse_name): Updated. * config/tc-nds32.h (MAX_RELAX_NUM): Extend it to 6. (enum nds32_relax_hint_type): Merge NDS32_RELAX_HINT_LA and NDS32_RELAX_HINT_LS into NDS32_RELAX_HINT_LALS. Add NDS32_RELAX_HINT_LA_PLT, NDS32_RELAX_HINT_LA_GOT and NDS32_RELAX_HINT_LA_GOTOFF. * config/tc-nds32.h (relax_ls_table): Add floating load/store to gp relax pattern. (hint_map, nds32_find_reloc_table): Likewise. * configure.ac: Define NDS32_LINUX_TOOLCHAIN. * configure: Regenerated. * config.in: Regenerated. * config/tc-nds32.h (enum nds32_ramp): Updated. (enum nds32_relax_hint_type): Likewise. * config/tc-nds32.c: Include "errno.h" and "limits.h". (relax_ls_table): Add TLS relax patterns. (nds32_elf_append_relax_relocs): Attach BFD_RELOC_NDS32_GROUP on each instructions of TLS patterns. (nds32_elf_record_fixup_exp): Updated. (nds32_apply_fix): Likewise. (suffix_table): Add TLSDESC suffix. binutils* testsuite/binutils-all/objcopy.exp: Set the unsupported reloc number from 215 to 255 for NDS32. bfd * elf32-nds32.c (nds32_elf_relax_loadstore): Remove the unused target features. (bfd_elf32_nds32_set_target_option): Remove the unused parameters. (nds32_elf_relax_piclo12, nds32_elf_relax_letlslo12, nds32_elf_relax_letlsadd, nds32_elf_relax_letlsls, nds32_elf_relax_pltgot_suff, nds32_elf_relax_got_suff nds32_elf_relax_gotoff_suff, calculate_plt_memory_address, calculate_plt_offset, calculate_got_memory_address, nds32_elf_check_dup_relocs): Removed. All callers changed. * elf32-nds32.h: Remove the unused macros and defines. (elf_nds32_link_hash_table): Remove the unused variable. (bfd_elf32_nds32_set_target_option): Update prototype. (nds32_elf_ex9_init): Removed. * elf32-nds32.c (nds32_convert_32_to_16): Updated. * elf32-nds32.c (HOWTO2, HOWTO3): Define new HOWTO macros to initialize array nds32_elf_howto_table in any order without lots of EMPTY_HOWTO. (nds32_reloc_map): Updated. * reloc.c: Add BFD_RELOC_NDS32_LSI. * bfd-in2.h: Regenerated. * bfd/libbfd.h: Regenerated. * elf32-nds32.c (nds32_elf_relax_howto_table): Add R_NDS32_LSI. (nds32_reloc_map): Likewise. (nds32_elf_relax_flsi): New function. (nds32_elf_relax_section): Support floating load/store relaxation. * elf32-nds32.c (NDS32_GUARD_SEC_P, elf32_nds32_local_gp_offset): New macro. (struct elf_nds32_link_hash_entry): New `offset_to_gp' field. (struct elf_nds32_obj_tdata): New `offset_to_gp' and `hdr_size' fields. (elf32_nds32_allocate_local_sym_info, nds32_elf_relax_guard, nds32_elf_is_target_special_symbol, nds32_elf_maybe_function_sym): New functions. (nds32_info_to_howto_rel): Add BFD_ASSERT. (bfd_elf32_bfd_reloc_type_table_lookup, nds32_elf_link_hash_newfunc, nds32_elf_link_hash_table_create, nds32_elf_relocate_section, nds32_elf_relax_loadstore, nds32_elf_relax_lo12, nds32_relax_adjust_label, bfd_elf32_nds32_set_target_option, nds32_fag_mark_relax): Updated. (nds32_elf_final_sda_base): Improve it to find the better gp value. (insert_nds32_elf_blank): Must consider `len' when inserting blanks. * elf32-nds32.h (bfd_elf32_nds32_set_target_option): Update prototype. (struct elf_nds32_link_hash_table): Add new variable `hyper_relax'. * elf32-nds32.c (elf32_nds32_allocate_dynrelocs): New function. (create_got_section): Likewise. (allocate_dynrelocs, nds32_elf_size_dynamic_sections, nds32_elf_relocate_section, nds32_elf_finish_dynamic_symbol): Updated. (nds32_elf_check_relocs): Fix the issue that the shared library may has TEXTREL entry in the dynamic section. (nds32_elf_create_dynamic_sections): Enable to call readonly_dynrelocs since the TEXTREL issue is fixed in the nds32_elf_check_relocs. (nds32_elf_finish_dynamic_sections): Update and add DT_RELASZ dynamic entry. (calculate_offset): Remove the unused parameter `pic_ext_target' and related codes. All callers changed. (elf_backend_dtrel_excludes_plt): Disable it temporarily since it will cause some errors for our test cases. * elf32-nds32.c (nds32_elf_merge_private_bfd_data): Allow to link the generic object. * reloc.c: Add TLS relocations. * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * elf32-nds32.h (struct section_id_list_t): New. (elf32_nds32_lookup_section_id, elf32_nds32_check_relax_group, elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New prototypes. (elf32_nds32_compute_jump_table_size, elf32_nds32_local_tlsdesc_gotent): New macro. (nds32_insertion_sort, bfd_elf32_nds32_set_target_option, elf_nds32_link_hash_table): Updated. * elf32-nds32.c (enum elf_nds32_tls_type): New. (struct elf32_nds32_relax_group_t, struct relax_group_list_t): New. (elf32_nds32_add_dynreloc, patch_tls_desc_to_ie, get_tls_type, fls, ones32, list_insert, list_insert_sibling, dump_chain, elf32_nds32_check_relax_group, elf32_nds32_lookup_section_id, elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New functions. (elf_nds32_obj_tdata): Add new fields. (elf32_nds32_relax_group_ptr, nds32_elf_local_tlsdesc_gotent): New macros. (nds32_elf_howto_table): Add TLS relocations. (nds32_reloc_map): Likewise. (nds32_elf_copy_indirect_symbol, nds32_elf_size_dynamic_sections, nds32_elf_finish_dynamic_symbol, elf32_nds32_allocate_local_sym_info, nds32_elf_relocate_section, bfd_elf32_nds32_set_target_option, nds32_elf_check_relocs, allocate_dynrelocs): Updated. (nds32_elf_relax_section): Call nds32_elf_unify_tls_model. (dtpoff_base): Rename it to `gottpof' and then update it. opcodes * nds32-asm.c (operand_fields): Remove the unused fields. (nds32_opcodes): Remove the unused instructions. * nds32-dis.c (nds32_ex9_info): Removed. (nds32_parse_opcode): Updated. (print_insn_nds32): Likewise. * nds32-asm.c (config.h, stdlib.h, string.h): New includes. (LEX_SET_FIELD, LEX_GET_FIELD): Update defines. (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table, build_opcode_hash_table): New functions. (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table, nds32_opcode_table): New. (hw_ktabs): Declare it to a pointer rather than an array. (build_hash_table): Removed. * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT, SYN_ROPT and upadte HW_GPR and HW_INT. * nds32-dis.c (keywords): Remove const. (match_field): New function. (nds32_parse_opcode): Updated. * disassemble.c (disassemble_init_for_target): Add disassemble_init_nds32. * nds32-dis.c (eum map_type): New. (nds32_private_data): Likewise. (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid, nds32_add_opcode_hash_table, disassemble_init_nds32): New functions. (print_insn_nds32): Updated. * nds32-asm.c (parse_aext_reg): Add new parameter. (parse_re, parse_re2, parse_aext_reg): Only reduced registers are allowed to use. All callers changed. * nds32-asm.c (keyword_usr, keyword_sr): Updated. (operand_fields): Add new fields. (nds32_opcodes): Add new instructions. (keyword_aridxi_mx): New keyword. * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX and NASM_ATTR_ZOL. (ALU2_1, ALU2_2, ALU2_3): New macros. * nds32-dis.c (nds32_filter_unknown_insn): Updated.
2018-09-17RISC-V: bge[u] should get higher priority than ble[u].Jim Wilson2-2/+6
2018-09-17 Kito Cheng <kito@andestech.com> gas/ * testsuite/gas/riscv/bge.d: New. * testsuite/gas/riscv/bge.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu5-13/+94
EVEX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64", "VMOVD r64/m64, xmm2", "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be encoded with EVEX.128. Set EVex=2 on EVEX.128 only vmovd and vmovq. gas/ PR gas/23670 * testsuite/gas/i386/evex-lig-2.d: New file. * testsuite/gas/i386/evex-lig-2.s: Likewise. * testsuite/gas/i386/x86-64-evex-lig-2.d: Likewise. * testsuite/gas/i386/x86-64-evex-lig-2.s: Likewise. * testsuite/gas/i386/i386.exp: Run evex-lig-2 and x86-64-evex-lig-2. opcodes/ PR gas/23670 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2, EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2. (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry. (EVEX_LEN_0F7E_P_1): Likewise. (EVEX_LEN_0F7E_P_2): Likewise. (EVEX_LEN_0FD6_P_2): Likewise. * i386-dis.c (USE_EVEX_LEN_TABLE): New. (EVEX_LEN_TABLE): Likewise. (EVEX_LEN_0F6E_P_2): New enum. (EVEX_LEN_0F7E_P_1): Likewise. (EVEX_LEN_0F7E_P_2): Likewise. (EVEX_LEN_0FD6_P_2): Likewise. (evex_len_table): New. (get_valid_dis386): Handle USE_EVEX_LEN_TABLE. * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq. * i386-tbl.h: Regenerated.
2018-09-17x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu4-18/+24
AVX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64" and "VMOVD r64/m64, xmm2" can only be encoded with VEX.128. Set Vex=1 on VEX.128 only vmovd and vmovq. gas/ PR gas/23665 * testsuite/gas/i386/avx-scalar.s: Remove vmovq and vmovd tests. * testsuite/gas/i386/x86-64-avx-scalar.s: Likewise. * testsuite/gas/i386/avx-scalar-intel.d: Updated. * testsuite/gas/i386/avx-scalar.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar.d: Likewise. * testsuite/gas/i386/i386.exp: Run avx-scalar2 and x86-64-avx-scalar2. * testsuite/gas/i386/avx-scalar-2.d: New file. * testsuite/gas/i386/avx-scalar-2.s: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-2.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-2.s: Likewise. opcodes/ PR gas/23665 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and VEX_LEN_0F7E_P_2 entries. * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq. * i386-tbl.h: Regenerated.
2018-09-17x86: Update disassembler for VexWIGH.J. Lu2-1563/+619
The VEX.W bit is ignored by some VEX instructions, aka WIG instructions. Update x86 disassembler to handle VEX WIG instructions. * i386-dis.c (VZERO_Fixup): Removed. (VZERO): Likewise. (VEX_LEN_0F10_P_1): Likewise. (VEX_LEN_0F10_P_3): Likewise. (VEX_LEN_0F11_P_1): Likewise. (VEX_LEN_0F11_P_3): Likewise. (VEX_LEN_0F2E_P_0): Likewise. (VEX_LEN_0F2E_P_2): Likewise. (VEX_LEN_0F2F_P_0): Likewise. (VEX_LEN_0F2F_P_2): Likewise. (VEX_LEN_0F51_P_1): Likewise. (VEX_LEN_0F51_P_3): Likewise. (VEX_LEN_0F52_P_1): Likewise. (VEX_LEN_0F53_P_1): Likewise. (VEX_LEN_0F58_P_1): Likewise. (VEX_LEN_0F58_P_3): Likewise. (VEX_LEN_0F59_P_1): Likewise. (VEX_LEN_0F59_P_3): Likewise. (VEX_LEN_0F5A_P_1): Likewise. (VEX_LEN_0F5A_P_3): Likewise. (VEX_LEN_0F5C_P_1): Likewise. (VEX_LEN_0F5C_P_3): Likewise. (VEX_LEN_0F5D_P_1): Likewise. (VEX_LEN_0F5D_P_3): Likewise. (VEX_LEN_0F5E_P_1): Likewise. (VEX_LEN_0F5E_P_3): Likewise. (VEX_LEN_0F5F_P_1): Likewise. (VEX_LEN_0F5F_P_3): Likewise. (VEX_LEN_0FC2_P_1): Likewise. (VEX_LEN_0FC2_P_3): Likewise. (VEX_LEN_0F3A0A_P_2): Likewise. (VEX_LEN_0F3A0B_P_2): Likewise. (VEX_W_0F10_P_0): Likewise. (VEX_W_0F10_P_1): Likewise. (VEX_W_0F10_P_2): Likewise. (VEX_W_0F10_P_3): Likewise. (VEX_W_0F11_P_0): Likewise. (VEX_W_0F11_P_1): Likewise. (VEX_W_0F11_P_2): Likewise. (VEX_W_0F11_P_3): Likewise. (VEX_W_0F12_P_0_M_0): Likewise. (VEX_W_0F12_P_0_M_1): Likewise. (VEX_W_0F12_P_1): Likewise. (VEX_W_0F12_P_2): Likewise. (VEX_W_0F12_P_3): Likewise. (VEX_W_0F13_M_0): Likewise. (VEX_W_0F14): Likewise. (VEX_W_0F15): Likewise. (VEX_W_0F16_P_0_M_0): Likewise. (VEX_W_0F16_P_0_M_1): Likewise. (VEX_W_0F16_P_1): Likewise. (VEX_W_0F16_P_2): Likewise. (VEX_W_0F17_M_0): Likewise. (VEX_W_0F28): Likewise. (VEX_W_0F29): Likewise. (VEX_W_0F2B_M_0): Likewise. (VEX_W_0F2E_P_0): Likewise. (VEX_W_0F2E_P_2): Likewise. (VEX_W_0F2F_P_0): Likewise. (VEX_W_0F2F_P_2): Likewise. (VEX_W_0F50_M_0): Likewise. (VEX_W_0F51_P_0): Likewise. (VEX_W_0F51_P_1): Likewise. (VEX_W_0F51_P_2): Likewise. (VEX_W_0F51_P_3): Likewise. (VEX_W_0F52_P_0): Likewise. (VEX_W_0F52_P_1): Likewise. (VEX_W_0F53_P_0): Likewise. (VEX_W_0F53_P_1): Likewise. (VEX_W_0F58_P_0): Likewise. (VEX_W_0F58_P_1): Likewise. (VEX_W_0F58_P_2): Likewise. (VEX_W_0F58_P_3): Likewise. (VEX_W_0F59_P_0): Likewise. (VEX_W_0F59_P_1): Likewise. (VEX_W_0F59_P_2): Likewise. (VEX_W_0F59_P_3): Likewise. (VEX_W_0F5A_P_0): Likewise. (VEX_W_0F5A_P_1): Likewise. (VEX_W_0F5A_P_3): Likewise. (VEX_W_0F5B_P_0): Likewise. (VEX_W_0F5B_P_1): Likewise. (VEX_W_0F5B_P_2): Likewise. (VEX_W_0F5C_P_0): Likewise. (VEX_W_0F5C_P_1): Likewise. (VEX_W_0F5C_P_2): Likewise. (VEX_W_0F5C_P_3): Likewise. (VEX_W_0F5D_P_0): Likewise. (VEX_W_0F5D_P_1): Likewise. (VEX_W_0F5D_P_2): Likewise. (VEX_W_0F5D_P_3): Likewise. (VEX_W_0F5E_P_0): Likewise. (VEX_W_0F5E_P_1): Likewise. (VEX_W_0F5E_P_2): Likewise. (VEX_W_0F5E_P_3): Likewise. (VEX_W_0F5F_P_0): Likewise. (VEX_W_0F5F_P_1): Likewise. (VEX_W_0F5F_P_2): Likewise. (VEX_W_0F5F_P_3): Likewise. (VEX_W_0F60_P_2): Likewise. (VEX_W_0F61_P_2): Likewise. (VEX_W_0F62_P_2): Likewise. (VEX_W_0F63_P_2): Likewise. (VEX_W_0F64_P_2): Likewise. (VEX_W_0F65_P_2): Likewise. (VEX_W_0F66_P_2): Likewise. (VEX_W_0F67_P_2): Likewise. (VEX_W_0F68_P_2): Likewise. (VEX_W_0F69_P_2): Likewise. (VEX_W_0F6A_P_2): Likewise. (VEX_W_0F6B_P_2): Likewise. (VEX_W_0F6C_P_2): Likewise. (VEX_W_0F6D_P_2): Likewise. (VEX_W_0F6F_P_1): Likewise. (VEX_W_0F6F_P_2): Likewise. (VEX_W_0F70_P_1): Likewise. (VEX_W_0F70_P_2): Likewise. (VEX_W_0F70_P_3): Likewise. (VEX_W_0F71_R_2_P_2): Likewise. (VEX_W_0F71_R_4_P_2): Likewise. (VEX_W_0F71_R_6_P_2): Likewise. (VEX_W_0F72_R_2_P_2): Likewise. (VEX_W_0F72_R_4_P_2): Likewise. (VEX_W_0F72_R_6_P_2): Likewise. (VEX_W_0F73_R_2_P_2): Likewise. (VEX_W_0F73_R_3_P_2): Likewise. (VEX_W_0F73_R_6_P_2): Likewise. (VEX_W_0F73_R_7_P_2): Likewise. (VEX_W_0F74_P_2): Likewise. (VEX_W_0F75_P_2): Likewise. (VEX_W_0F76_P_2): Likewise. (VEX_W_0F77_P_0): Likewise. (VEX_W_0F7C_P_2): Likewise. (VEX_W_0F7C_P_3): Likewise. (VEX_W_0F7D_P_2): Likewise. (VEX_W_0F7D_P_3): Likewise. (VEX_W_0F7E_P_1): Likewise. (VEX_W_0F7F_P_1): Likewise. (VEX_W_0F7F_P_2): Likewise. (VEX_W_0FAE_R_2_M_0): Likewise. (VEX_W_0FAE_R_3_M_0): Likewise. (VEX_W_0FC2_P_0): Likewise. (VEX_W_0FC2_P_1): Likewise. (VEX_W_0FC2_P_2): Likewise. (VEX_W_0FC2_P_3): Likewise. (VEX_W_0FD0_P_2): Likewise. (VEX_W_0FD0_P_3): Likewise. (VEX_W_0FD1_P_2): Likewise. (VEX_W_0FD2_P_2): Likewise. (VEX_W_0FD3_P_2): Likewise. (VEX_W_0FD4_P_2): Likewise. (VEX_W_0FD5_P_2): Likewise. (VEX_W_0FD6_P_2): Likewise. (VEX_W_0FD7_P_2_M_1): Likewise. (VEX_W_0FD8_P_2): Likewise. (VEX_W_0FD9_P_2): Likewise. (VEX_W_0FDA_P_2): Likewise. (VEX_W_0FDB_P_2): Likewise. (VEX_W_0FDC_P_2): Likewise. (VEX_W_0FDD_P_2): Likewise. (VEX_W_0FDE_P_2): Likewise. (VEX_W_0FDF_P_2): Likewise. (VEX_W_0FE0_P_2): Likewise. (VEX_W_0FE1_P_2): Likewise. (VEX_W_0FE2_P_2): Likewise. (VEX_W_0FE3_P_2): Likewise. (VEX_W_0FE4_P_2): Likewise. (VEX_W_0FE5_P_2): Likewise. (VEX_W_0FE6_P_1): Likewise. (VEX_W_0FE6_P_2): Likewise. (VEX_W_0FE6_P_3): Likewise. (VEX_W_0FE7_P_2_M_0): Likewise. (VEX_W_0FE8_P_2): Likewise. (VEX_W_0FE9_P_2): Likewise. (VEX_W_0FEA_P_2): Likewise. (VEX_W_0FEB_P_2): Likewise. (VEX_W_0FEC_P_2): Likewise. (VEX_W_0FED_P_2): Likewise. (VEX_W_0FEE_P_2): Likewise. (VEX_W_0FEF_P_2): Likewise. (VEX_W_0FF0_P_3_M_0): Likewise. (VEX_W_0FF1_P_2): Likewise. (VEX_W_0FF2_P_2): Likewise. (VEX_W_0FF3_P_2): Likewise. (VEX_W_0FF4_P_2): Likewise. (VEX_W_0FF5_P_2): Likewise. (VEX_W_0FF6_P_2): Likewise. (VEX_W_0FF7_P_2): Likewise. (VEX_W_0FF8_P_2): Likewise. (VEX_W_0FF9_P_2): Likewise. (VEX_W_0FFA_P_2): Likewise. (VEX_W_0FFB_P_2): Likewise. (VEX_W_0FFC_P_2): Likewise. (VEX_W_0FFD_P_2): Likewise. (VEX_W_0FFE_P_2): Likewise. (VEX_W_0F3800_P_2): Likewise. (VEX_W_0F3801_P_2): Likewise. (VEX_W_0F3802_P_2): Likewise. (VEX_W_0F3803_P_2): Likewise. (VEX_W_0F3804_P_2): Likewise. (VEX_W_0F3805_P_2): Likewise. (VEX_W_0F3806_P_2): Likewise. (VEX_W_0F3807_P_2): Likewise. (VEX_W_0F3808_P_2): Likewise. (VEX_W_0F3809_P_2): Likewise. (VEX_W_0F380A_P_2): Likewise. (VEX_W_0F380B_P_2): Likewise. (VEX_W_0F3817_P_2): Likewise. (VEX_W_0F381C_P_2): Likewise. (VEX_W_0F381D_P_2): Likewise. (VEX_W_0F381E_P_2): Likewise. (VEX_W_0F3820_P_2): Likewise. (VEX_W_0F3821_P_2): Likewise. (VEX_W_0F3822_P_2): Likewise. (VEX_W_0F3823_P_2): Likewise. (VEX_W_0F3824_P_2): Likewise. (VEX_W_0F3825_P_2): Likewise. (VEX_W_0F3828_P_2): Likewise. (VEX_W_0F3829_P_2): Likewise. (VEX_W_0F382A_P_2_M_0): Likewise. (VEX_W_0F382B_P_2): Likewise. (VEX_W_0F3830_P_2): Likewise. (VEX_W_0F3831_P_2): Likewise. (VEX_W_0F3832_P_2): Likewise. (VEX_W_0F3833_P_2): Likewise. (VEX_W_0F3834_P_2): Likewise. (VEX_W_0F3835_P_2): Likewise. (VEX_W_0F3837_P_2): Likewise. (VEX_W_0F3838_P_2): Likewise. (VEX_W_0F3839_P_2): Likewise. (VEX_W_0F383A_P_2): Likewise. (VEX_W_0F383B_P_2): Likewise. (VEX_W_0F383C_P_2): Likewise. (VEX_W_0F383D_P_2): Likewise. (VEX_W_0F383E_P_2): Likewise. (VEX_W_0F383F_P_2): Likewise. (VEX_W_0F3840_P_2): Likewise. (VEX_W_0F3841_P_2): Likewise. (VEX_W_0F38DB_P_2): Likewise. (VEX_W_0F3A08_P_2): Likewise. (VEX_W_0F3A09_P_2): Likewise. (VEX_W_0F3A0A_P_2): Likewise. (VEX_W_0F3A0B_P_2): Likewise. (VEX_W_0F3A0C_P_2): Likewise. (VEX_W_0F3A0D_P_2): Likewise. (VEX_W_0F3A0E_P_2): Likewise. (VEX_W_0F3A0F_P_2): Likewise. (VEX_W_0F3A21_P_2): Likewise. (VEX_W_0F3A40_P_2): Likewise. (VEX_W_0F3A41_P_2): Likewise. (VEX_W_0F3A42_P_2): Likewise. (VEX_W_0F3A62_P_2): Likewise. (VEX_W_0F3A63_P_2): Likewise. (VEX_W_0F3ADF_P_2): Likewise. (VEX_LEN_0F77_P_0): New. (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11, PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E, PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52, PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59, PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C, PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F, PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F, PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4, PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2, PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6, PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C, PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2, PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2, PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5, PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE, PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1, PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4, PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8, PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB, PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE, PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2, PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5, PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832, PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries. (vex_table): Update VEX 0F28 and 0F29 entries. (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3, VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0, VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2, VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1, VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3, VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1, VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3, VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1, VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3, VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and VEX_LEN_0F3A0B_P_2 entries. (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1, VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1, VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0, VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2, VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15, VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1, VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29, VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0, VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1, VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1, VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1, VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1, VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1, VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2, VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3, VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3, VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3, VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3, VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2, VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2, VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2, VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2, VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3, VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2, VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2, VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2, VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2, VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3, VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1, VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0, VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3, VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2, VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2, VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2, VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2, VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2, VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2, VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3, VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2, VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2, VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0, VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2, VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2, VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2, VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2, VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2, VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2, VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2, VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2, VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2, VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2, VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2, VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0, VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2, VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2, VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2, VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2, VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2, VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2, VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2, VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2, VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2, VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2, VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and VEX_W_0F3ADF_P_2 entries. (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50, MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2, MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
2018-09-17x86: Replace VexW=3 with VexWIGH.J. Lu2-468/+475
* i386-opc.tbl (VexWIG): New. Replace VexW=3 with VexWIG.
2018-09-15x86: Set VexW=3 on AVX vrsqrtssH.J. Lu3-2/+7
AVX vrsqrtss is a VEX WIG instruction. * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss. * i386-tbl.h: Regenerated.
2018-09-15x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu4-6/+12
AVX "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be encoded with VEX.128. Set Vex=1 on VEX.128 only vmovq and update assembler tests. gas/ PR gas/23665 * testsuite/gas/i386/avx-scalar-intel.d: Updated. * testsuite/gas/i386/avx-scalar.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar.d: Likewise. opcodes/ PR gas/23665 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and VEX_LEN_0FD6_P_2 entries. * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq. * i386-tbl.h: Regenerated.
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu4-932/+941
Add VEXWIG, defined as 3, to indicate that the VEX.W/EVEX.W bit is ignored by such VEX/EVEX instructions, aka WIG instructions. Set VexW=3 on VEX/EVEX WIG instructions. Update assembler to check VEXWIG when setting the VEX.W bit. gas/ PR gas/23642 * config/tc-i386.c (build_vex_prefix): Check VEXWIG when setting the VEX.W bit. (build_evex_prefix): Check VEXWIG when setting the EVEX.W bit. opcodes/ PR gas/23642 * i386-opc.h (VEXWIG): New. * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions. * i386-tbl.h: Regenerated.
2018-09-14x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu3-2/+22
Update x86 disassembler to handle the unsupported static rounding in vcvt[u]si2sd in 32-bit mode. gas/ PR binutils/23655 * testsuite/gas/i386/evex.d: Updated. opcodes/ PR binutils/23655 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for vcvtsi2sd%LQ and vcvtusi2sd%LQ. * i386-dis.c (EXxEVexR64): New. (evex_rounding_64_mode): Likewise. (OP_Rounding): Handle evex_rounding_64_mode.
2018-09-14x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu3-4/+23
Update x86 disassembler to ignore the EVEX.W bit in EVEX vcvt[u]si2s[sd] instructions in 32-bit mode. gas/ PR binutils/23655 * testsuite/gas/i386/evex.d: New file. * testsuite/gas/i386/evex.s: Likewise. * testsuite/gas/i386/i386.exp: Run evex. opcodes/ PR binutils/23655 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ. * i386-dis.c (Edqa): New. (dqa_mode): Likewise. (intel_operand_size): Handle dqa_mode as m_mode. (OP_E_register): Handle dqa_mode as dq_mode. (OP_E_memory): Set shift for dqa_mode based on address_mode.
2018-09-14i386: Reformat OP_E_memoryH.J. Lu2-2/+6
* i386-dis.c (OP_E_memory): Reformat.
2018-09-14x86: fold CRC32 templatesJan Beulich3-45/+12
Just like other insns having byte and word forms, these can also make use of the W modifier, which at the same time allows simplifying some other code a little bit.
2018-09-13x86: Remove VexW=1 from WIG VEX movq and vmovqH.J. Lu2-8/+8
Put back changes lost in commit 41d1ab6a6d96937fd0db04e53746f93f53687807.
2018-09-13i386: Update VexW field for VEX instructionsH.J. Lu3-36/+44
1. Mark VEX.W0 VEX instructions with VexW=1. 2. Mark VEX.W1 VEX instructions with VexW=2. 3. Remove VexW=1 from WIG VEX instructions. * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd, pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd. Add VexW=2 to VEX.W1 VEX movd, movq, pextrq, pinsrq, vmod, vmovq, vpextrq and vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq. * i386-tbl.h: Regenerated.
2018-09-13x86: drop bogus IgnoreSize from a few further insnsJan Beulich3-52/+61
2018-09-13x86: drop bogus IgnoreSize from AVX512_4* insnsJan Beulich3-12/+18
2018-09-13x86: drop bogus IgnoreSize from AVX512DQ insnsJan Beulich3-96/+102
2018-09-13x86: drop bogus IgnoreSize from AVX512BW insnsJan Beulich3-78/+84
2018-09-13x86: drop bogus IgnoreSize from AVX512VL insnsJan Beulich3-26/+32
2018-09-13x86: drop bogus IgnoreSize from AVX512ER insnsJan Beulich3-32/+38
2018-09-13x86: drop bogus IgnoreSize from AVX512F insnsJan Beulich3-742/+748
2018-09-13x86: drop bogus IgnoreSize from SHA insnsJan Beulich3-16/+21
2018-09-13x86: drop bogus IgnoreSize from XOP and SSE4a insnsJan Beulich3-266/+271
2018-09-13x86: drop bogus IgnoreSize from AVX2 insnsJan Beulich3-238/+244
2018-09-13x86: drop bogus IgnoreSize from AVX insnsJan Beulich3-256/+262
2018-09-13x86: drop bogus IgnoreSize from GNFI insnsJan Beulich3-12/+17
2018-09-13x86: drop bogus IgnoreSize from PCLMUL/VPCLMUL insnsJan Beulich3-32/+37
2018-09-13x86: drop bogus IgnoreSize from AES/VAES insnsJan Beulich3-44/+49
2018-09-13x86: drop bogus IgnoreSize from SSE4.2 insnsJan Beulich3-20/+26
2018-09-13x86: drop bogus IgnoreSize from SSE4.1 insnsJan Beulich3-126/+132
2018-09-13x86: drop bogus IgnoreSize from SSSE3 insnsJan Beulich3-64/+70
2018-09-13x86: drop bogus IgnoreSize from SSE3 insnsJan Beulich3-36/+41
2018-09-13x86: drop bogus IgnoreSize from SSE2 insnsJan Beulich3-416/+421
2018-09-13x86: drop bogus IgnoreSize from SSE insnsJan Beulich3-118/+123
2018-09-13x86: drop unnecessary {,No}Rex64Jan Beulich3-10/+16
2018-09-13x86: also allow D on 3-operand insnsJan Beulich3-96/+18
For now this is just for VMOVS{D,S}.
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich4-1277/+165
Various moves come in load and store forms, and just like on the GPR and FPU sides there would better be only one pattern. In some cases this is not feasible because the opcodes are too different, but quite a few cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse operand handling there simply needs to match "straight" operand one), and fix a long standing, but so far only latent bug with when to zap found_reverse_match. Also once again drop IgnoreSize where pointlessly applied to templates touched anyway as well as *word when redundant with Reg*.
2018-09-13x86-64: bndmk, bndldx, and bndstx don't allow RIP-relative addressingJan Beulich2-3/+21
2018-09-08S12Z: Make disassebler work for --enable-targets=all config.John Darrington2-0/+5
opcodes/ * disassemble.c (ARCH_s12z): Define if ARCH_all.
2018-08-31RISC-V: Correct the requirement of compressed floating point instructionsJim Wilson2-16/+21
2018-08-31 Kito Cheng <kito@andestech.com> gas/ * testsuite/gas/riscv/c-fld-fsd-fail.d: New. * testsuite/gas/riscv/c-fld-fsd-fail.l: Likewise. * testsuite/gas/riscv/c-fld-fsd-fail.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for compressed floating point instructions.
2018-08-30RISC-V: Allow instruction require more than one extensionJim Wilson3-630/+636
2018-08-29 Kito Cheng <kito@andestech.com> gas/ * config/tc-riscv.c (riscv_subset_supports): New argument: xlen_required. (riscv_multi_subset_supports): New function, able to check more than one extension. (riscv_ip): Use riscv_multi_subset_supports instead of riscv_subset_supports. (riscv_set_arch): Update call-site for riscv_subset_supports. (riscv_after_parse_args): Likewise. include/ *opcode/riscv.h (MAX_SUBSET_NUM): New. (riscv_opcode): Add xlen_requirement field and change type of subset. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Check XLEN by riscv_opcode.xlen_requirement. * riscv-opc.c (riscv_opcodes): Update for struct change.
2018-08-29sparc/leon: add support for partial write psr instructionMartin Aberg2-0/+13
Partial write %PSR (PWRPSR) is a SPARC V8e option that allows the WRPSR instruction to only affect the %PSR.ET field. When available it is enabled by setting the rd field of the WRPSR instruction to a value other than 0. For Leon processors with support for partial write %PSR (currently GR740 and GR716) the rd value must be 1. opcodes/ChangeLog: 2018-08-29 Martin Aberg <maberg@gaisler.com> * sparc-opc.c (sparc_opcodes): Add Leon specific partial write psr (PWRPSR) instruction. gas/ChangeLog: 2018-08-29 Daniel Cederman <cederman@gaisler.com> * testsuite/gas/sparc/leon.d: New test. * testsuite/gas/sparc/leon.s: New test. * testsuite/gas/sparc/sparc.exp: Execute the pwrpsr test.
2018-08-29[MIPS] Add Loongson 2K1000 proccessor support.Chenghua Xu2-0/+9
bfd/ * archures.c (bfd_architecture): New machine bfd_mach_mips_gs264e. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_GS264E. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Map bfd_mach_mips_gs264e to bfd_mach_mips_gs464e extension. binutils/ * NEWS: Mention Loongson 2K1000 proccessor support. * readelf.c (get_machine_flags): Handle gs264e. elfcpp/ * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E. (mips_cpu_info_table): Add gs264e descriptors. * doc/as.texi (march table): Add gs264e. include/ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E. * opcode/mips.h (CPU_XXX): New CPU_GS264E. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination gs264e and gs464e. opcodes/ * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
2018-08-29[MIPS] Add Loongson 3A2000/3A3000 proccessor support.Chenghua Xu2-0/+9
bfd/ * archures.c (bfd_architecture): New machine bfd_mach_mips_gs464e. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_GS464E. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Map bfd_mach_mips_gs464e to bfd_mach_mips_gs464 extension. binutils/ * NEWS: Mention Loongson 3A2000/3A3000 proccessor support. * readelf.c (get_machine_flags): Handle gs464e. elfcpp/ * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E. (mips_cpu_info_table): Add gs464e descriptors. * doc/as.texi (march table): Add gs464e. include/ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E. * opcode/mips.h (CPU_XXX): New CPU_GS464E. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination gs464e and gs464. opcodes/ * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
2018-08-29[MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu3-2/+14
bfd/ * archures.c (bfd_architecture): Rename bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Likewise. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Likewise. (bfd_mips_isa_ext_mach): Likewise. (bfd_mips_isa_ext): Likewise. (print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A. binutils/ * NEWS: Mention Loongson 3A1000 proccessor support. * readelf.c (get_machine_flags): Rename loongson-3a to gs464. (print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A. elfcpp/ * mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to E_MIPS_MACH_GS464. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename CPU_LOONGSON_3A to CPU_GS464. (mips_cpu_info_table): Add gs464 descriptors, Keep loongson3a as an alias of gs464 for compatibility. * doc/as.texi (march table): Rename loongson3a to gs464. * testsuite/gas/mips/loongson-3a-mmi.d: Set "ISA Extension" flag to None. gold/ * mips.cc (Mips_mach, add_machine_extensions, elf_mips_mach): Rename loongson3a to gs464. (mips_isa_ext_mach, mips_isa_ext): Delete loongson3a. (infer_abiflags): Use ases instead of isa_ext for infer ABI flags. (elf_mips_mach_name): Rename loongson3a to gs464. include/ * elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to E_MIPS_MACH_GS464. (AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A. * opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A. (CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464. * opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a to gs464. opcodes/ * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep loongson3a as an alias of gs464 for compatibility. * mips-opc.c (mips_opcodes): Change Comments.
2018-08-29[MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu3-0/+26
bfd/ * elfxx-mips.c (print_mips_ases): Add Loongson EXT2 extension. binutils/ * readelf.c (print_mips_ases): Add Loongson EXT2 extension. gas/ * NEWS: Mention Loongson EXTensions R2 (EXT2) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT2 and OPTION_NO_LOONGSON_EXT2. (md_longopts): Likewise. (mips_ases): Define availability for EXT. (mips_convert_ase_flags): Map ASE_LOONGSON_EXT2 to AFL_ASE_LOONGSON_EXT2. (md_show_usage): Add help for -mloongson-ext2 and -mno-loongson-ext2. * doc/as.texi: Document -mloongson-ext2, -mno-loongson-ext2. * doc/c-mips.texi: Document -mloongson-ext2, -mno-loongson-ext2, .set loongson-ext2 and .set noloongson-ext2. * testsuite/gas/mips/loongson-ext2.d: New test. * testsuite/gas/mips/loongson-ext2.s: New test. * testsuite/gas/mips/mips.exp: Run loongson-ext2 test. include/ * elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2. * opcode/mips.h (ASE_LOONGSON_EXT2): New macro. opcodes/ * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext option. (print_mips_disassembler_options): Document -M loongson-ext. * mips-opc.c (LEXT2): New macro. (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
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