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2005-03-07 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.Aldy Hernandez2-1/+5
2005-03-05Regenerate .pot filesAlan Modra2-111/+115
2005-03-032005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>Ramana Radhakrishnan2-29/+54
* opcodes/arc-dis.c:Add enum a4_decoding_class. (dsmOneArcInst): Use the enum values for the decoding class Remove redundant case in the switch for decodingClass value 11
2005-03-03update copyright datesAlan Modra43-47/+55
2005-03-02gas/Jan Beulich2-4/+19
2005-03-02 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (build_modrm_byte): Add lock prefix for cr8...15 accesses. (parse_register): Allow cr8...15 in all modes. gas/testsuite/ 2005-03-02 Jan Beulich <jbeulich@novell.com> * gas/i386/cr-err.[ls]: New. * gas/i386/crx.[ds]: New. * gas/i386/i386.exp: Run new tests. opcodes/ 2005-03-02 Jan Beulich <jbeulich@novell.com> * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15 accesses. (OP_C): Consider lock prefix in non-64-bit modes.
2005-02-24 * cris-dis.c (format_hex): Remove ineffective warning fix.Alan Modra4-7/+12
* crx-dis.c (make_instruction): Warning fix. * frv-asm.c: Regenerate.
2005-02-23Fix compile time warnings generated by gcc 4.0Nick Clifton17-312/+307
2005-02-23(make_instruction): Move argument structure into inner scope and ensure thatNick Clifton2-1/+8
all of its fields are initialised before they are used.
2005-02-22 * arc-ext.c: Warning fixes.Alan Modra9-288/+302
* arc-ext.h: Likewise. * cgen-opc.c: Likewise. * ia64-gen.c: Likewise. * maxq-dis.c: Likewise. * ns32k-dis.c: Likewise. * w65-dis.c: Likewise. * ia64-asmtab.c: Regenerate.
2005-02-22Regenerate cgen filesAlan Modra30-51/+83
2005-02-21 * Makefile.am: Run "make dep-am"Alan Modra3-16/+22
* Makefile.in: Regenerate.
2005-02-15Fix compile time warning messagesNick Clifton36-662/+667
2005-02-142005-02-14 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-4/+14
* dis-buf.c (perror_memory): Use sprintf_vma to print out address.
2005-02-11Fix compile time warning building iq2000-asm.cNick Clifton2-3/+5
2005-02-11Regenerate frv-dis.c in order to fix a compile time warning.Nick Clifton2-1/+5
2005-02-08cgen/ChangeLog:Jim Blandy4-4/+14
2005-02-07 Jim Blandy <jimb@redhat.com> * cgen-opc.scm: Don't load fixup.scm here. (See corresponding changes in the opcodes directory.) opcodes/ChangeLog: 2005-02-07 Jim Blandy <jimb@redhat.com> * Makefile.am (CGEN): Load guile.scm before calling the main application script. * Makefile.in: Regenerated. * cgen.sh: Be prepared for the 'cgen' argument to contain spaces. Simply pass the cgen-opc.scm path to ${cgen} as its first argument; ${cgen} itself now contains the '-s', or whatever is appropriate for the Scheme being used.
2005-01-312005-01-31 Andrew Cagney <cagney@gnu.org>Andrew Cagney2-5/+11
* gettext.m4: Only set ENABLE_NLS when gettext is present.
2005-01-31gas/Jan Beulich5-4949/+5982
2005-01-31 Jan Beulich <jbeulich@novell.com> * config/tc-ia64.c (parse_operands): Also handle alloc without first input being ar.pfs. gas/testsuite/ 2005-01-31 Jan Beulich <jbeulich@novell.com> * gas/ia64/pseudo.[ds]: New. * gas/ia64/ia64.exp: Run new test. opcodes/ 2005-01-31 Jan Beulich <jbeulich@novell.com> * ia64-gen.c (NELEMS): Define. (shrink): Generate alias with missing second predicate register when opcode has two outputs and these are both predicates. * ia64-opc-i.c (FULL17): Define. (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17 here to generate output template. (TBITCM, TNATCM): Undefine after use. * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as first input. Add ld16 aliases without ar.csd as second output. Add st16 aliases without ar.csd as second input. Add cmpxchg aliases without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/ ar.ccv as third/fourth inputs. Consolidate through... (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8, CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define. * ia64-asmtab.c: Regenerate.
2005-01-272005-01-27 Andrew Cagney <cagney@gnu.org>Andrew Cagney2-2/+6
* gettext.m4: Don't use NONE as a default for CATOBJEXT.
2005-01-25bfd/ChangeLog:Alexandre Oliva8-200/+634
2004-12-10 Alexandre Oliva <aoliva@redhat.com> * elf32-frv.c (elf32_frv_relocate_section): Force local binding for TLSMOFF. * reloc.c: Add R_FRV_TLSMOFF. * elf32-frv.c (elf32_frv_howto_table): Likewise. (frv_reloc_map, frv_reloc_type_lookup): Map it. (elf32_frv_relocate_section): Handle it. (elf32_frv_check_relocs): Likewise. * libbfd.h, bfd-in2.h: Rebuilt. 2004-11-26 Alexandre Oliva <aoliva@redhat.com> * elf32-frv.c (_frvfdpic_emit_got_relocs_plt_entries): Don't crash when given an undefweak TLS symbol. Fix constant TLS PLT entries such that they return the constant in gr9. (_frvfdpic_relax_tls_entries): Don't crash for undefweak TLS symbols. (_frvfdpic_size_got_plt): Set _cooked_size of dynamic sections. too, such that they shrink on relaxation. (elf32_frvfdpic_finish_dynamic_sections): Check __ROFIXUP_END__ as marking the position right past the _GLOBAL_OFFSET_TABLE_ value. (_frvfdpic_assign_plt_entries): Shrink constant TLS PLT entries if we can guarantee the use of 16-bit constants. 2004-11-10 Alexandre Oliva <aoliva@redhat.com> Introduce TLS support for FR-V FDPIC. * reloc.c: Add TLS relocations. * elf32-frv.c (elf32_frv_howto_table): Add TLS relocations. (elf32_frv_rel_tlsdesc_value_howto): New. (elf32_frv_rel_tlsoff_howto): New. (frv_reloc_map): Add new mappings. (struct frvfdpic_elf_link_hash_table): Add pointer to summary reloc information. (frvfdpic_dynamic_got_plt_info): New. (frvfdpic_plt_tls_ret_offset): New. (ELF_DYNAMIC_INTERPRETER, DEFAULT_STACK_SIZE): Move earlier. (struct _frvfdpic_dynamic_got_info): Likewise. Add TLS members. (struct _frvfdpic_dynamic_got_plt_info): Likewise. (FRVFDPIC_SYM_LOCAL): Regard symbols defined in the absolute section as local. (struct frvfdpic_relocs_info): Add TLS fields. (frvfdpic_relocs_info_hash): Warning clean up. (frvfdpic_relocs_info_find): Initialize tlsplt_entry. (frvfdpic_pic_merge_early_relocs_info): Merge TLS fields. (FRVFDPIC_TLS_BIAS): Define. (tls_biased_base): New. (_frvfdpic_emit_got_relocs_plt_entries): Deal with TLS relocations. (frv_reloc_type_lookup): Likewise. (frvfdpic_info_to_howto_rel): Likewise. (elf32_frv_relocate_section): Likewise. (_frv_create_got_section): Create the PLT section here. (elf32_frvfdpic_create_dynamic_sections): Not here. (_frvfdpic_count_nontls_entries): Move out of... (_frvfdpic_count_got_plt_entries): ... here. (_frvfdpic_count_tls_entries): Likewise. Add TLS support. (_frvfdpic_count_relocs_fixups): Likewise. Add relaxation support. (_frvfdpic_relax_tls_entries): New. (_frvfdpic_compute_got_alloc_data): Add TLS support. (_frvfdpic_get_tlsdesc_entry): New. (_frvfdpic_assign_got_entries): Add TLS support. (_frvfdpic_assign_plt_entries): Likewise. (_frvfdpic_reset_got_plt_entries): New. (_frvfdpic_size_got_plt): Move out of... (elf32_frvfdpic_size_dynamic_sections): ... here. (_frvfdpic_relax_got_plt_entries): New. (elf32_frvfdpic_relax_section): New. (elf32_frvfdpic_finish_dynamic_sections): Add TLS sanity check. (elf32_frv_check_relocs): Add TLS support. (bfd_elf32_bfd_relax_section): Define for FDPIC. * libbfd.h, bfd-in2.h: Rebuilt. cpu/ChangeLog: 2004-11-10 Alexandre Oliva <aoliva@redhat.com> * frv.cpu: Add support for TLS annotations in loads and calll. * frv.opc (parse_symbolic_address): New. (parse_ldd_annotation): New. (parse_call_annotation): New. (parse_ld_annotation): New. (parse_ulo16, parse_uslo16): Use parse_symbolic_address. Introduce TLS relocations. (parse_d12, parse_s12, parse_u12): Likewise. (parse_uhi16): Likewise. Fix constant checking on 64-bit host. (parse_call_label, print_at): New. gas/ChangeLog: * config/tc-frv.c (md_apply_fix3): Mark TLS symbols as such. 2004-12-10 Alexandre Oliva <aoliva@redhat.com> * config/tc-frv.c (frv_pic_ptr): Add tlsmoff support. 2004-11-10 Alexandre Oliva <aoliva@redhat.com> * cgen.c (gas_cgen_parse_operand): Handle CGEN_PARSE_OPERAND_SYMBOLIC. * config/tc-frv.c (md_cgen_lookup_reloc): Handle TLS relocations. (frv_force_relocation): Likewise. Fix handling of PIC relocations. (md_apply_fix3): Likewise. include/elf/ChangeLog: 2004-12-10 Alexandre Oliva <aoliva@redhat.com> * frv.h: Add R_FRV_TLSMOFF. 2004-11-10 Alexandre Oliva <aoliva@redhat.com> * frv.h: Add TLS relocations. include/opcode/ChangeLog: 2004-11-10 Alexandre Oliva <aoliva@redhat.com> * cgen.h (enum cgen_parse_operand_type): Add CGEN_PARSE_OPERAND_SYMBOLIC. ld/testsuite/ChangeLog: * ld-frv/fdpic.exp: Add -mfdpic to ASFLAGS. * ld-frv/tls.exp: Likewise. 2004-11-26 Alexandre Oliva <aoliva@redhat.com> * ld-frv/tls-3.s: New. * ld-frv/tls-static-3.d: New. * ld-frv/tls-dynamic-3.d: New. * ld-frv/tls-pie-3.d: New. * ld-frv/tls-shared-3.d: New. * ld-frv/tls-relax-static-3.d: New. * ld-frv/tls-relax-dynamic-3.d: New. * ld-frv/tls-relax-pie-3.d: New. * ld-frv/tls-relax-shared-3.d: New. * ld-frv/tls.exp: Run the new tests. * ld-frv/tls-dynamic-2.d: Adjust for improved relaxation. * ld-frv/tls-relax-dynamic-2.d: Likewise. * ld-frv/tls-relax-initial-shared-2.d: Likewise. 2004-11-10 Alexandre Oliva <aoliva@redhat.com> * ld-frv/tls-1-dep.s: New. * ld-frv/tls-1-shared.lds: New. * ld-frv/tls-1.s: New. * ld-frv/tls-2.s: New. * ld-frv/tls-dynamic-1.d: New. * ld-frv/tls-dynamic-2.d: New. * ld-frv/tls-initial-shared-2.d: New. * ld-frv/tls-pie-1.d: New. * ld-frv/tls-relax-dynamic-1.d: New. * ld-frv/tls-relax-dynamic-2.d: New. * ld-frv/tls-relax-initial-shared-2.d: New. * ld-frv/tls-relax-pie-1.d: New. * ld-frv/tls-relax-shared-1.d: New. * ld-frv/tls-relax-shared-2.d: New. * ld-frv/tls-relax-static-1.d: New. * ld-frv/tls-shared-1-fail.d: New. * ld-frv/tls-shared-1.d: New. * ld-frv/tls-shared-2.d: New. * ld-frv/tls-static-1.d: New. * ld-frv/tls.exp: New. * ld-frv/fdpic-pie-1.d: Adjust for 64-bit host. * ld-frv/fdpic-pie-2.d: Likewise. * ld-frv/fdpic-pie-6.d: Likewise. * ld-frv/fdpic-pie-7.d: Likewise. * ld-frv/fdpic-pie-8.d: Likewise. * ld-frv/fdpic-shared-1.d: Likewise. * ld-frv/fdpic-shared-2.d: Likewise. * ld-frv/fdpic-shared-3.d: Likewise. * ld-frv/fdpic-shared-4.d: Likewise. * ld-frv/fdpic-shared-5.d: Likewise. * ld-frv/fdpic-shared-6.d: Likewise. * ld-frv/fdpic-shared-7.d: Likewise. * ld-frv/fdpic-shared-8.d: Likewise. * ld-frv/fdpic-shared-local-2.d: Likewise. * ld-frv/fdpic-shared-local-8.d: Likewise. * ld-frv/fdpic-static-1.d: Likewise. * ld-frv/fdpic-static-2.d: Likewise. * ld-frv/fdpic-static-6.d: Likewise. * ld-frv/fdpic-static-7.d: Likewise. * ld-frv/fdpic-static-8.d: Likewise. opcodes/ChangeLog: 2004-11-10 Alexandre Oliva <aoliva@redhat.com> * frv-asm.c: Rebuilt. * frv-desc.c: Rebuilt. * frv-desc.h: Rebuilt. * frv-dis.c: Rebuilt. * frv-ibld.c: Rebuilt. * frv-opc.c: Rebuilt. * frv-opc.h: Rebuilt.
2005-01-242005-01-24 Andrew Cagney <cagney@gnu.org>Andrew Cagney2-2/+8
* gettext.m4: Only fall back to ../intl/ when it's present.
2005-01-21 2005-01-21 Fred Fish <fnf@specifixinc.com>Fred Fish3-16/+23
* mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS. Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. * mips-dis.c: Ditto.
2005-01-20 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.Alan Modra2-3/+7
2005-01-19 2005-01-19 Fred Fish <fnf@specifixinc.com>Fred Fish4-1191/+1220
* mips-dis.c (no_aliases): New disassembly option flag. (set_default_mips_dis_options): Init no_aliases to zero. (parse_mips_dis_option): Handle no-aliases option. (print_insn_mips): Ignore table entries that are aliases if no_aliases is set. (print_insn_mips16): Ditto. * mips-opc.c (mips_builtin_opcodes): Add initializer column for new pinfo2 member and add INSN_ALIAS initializers as needed. Also move WR_MACC and RD_MACC initializers from pinfo to pinfo2. * mips16-opc.c (mips16_opcodes): Ditto.
2005-01-17Fix SH2A machine variants in order to correctly select instruction inheritanceNick Clifton2-277/+333
2005-01-122005-01-12 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-2/+6
* i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
2005-01-12gas/testsuite/H.J. Lu2-1/+7
2005-01-12 H.J. Lu <hongjiu.lu@intel.com> * i386/i386.exp: Run "sib". * gas/i386/sib.d: New file. * gas/i386/sib.s: Likewise. opcodes/ 2005-01-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
2005-01-10binutils/:Andreas Schwab2-1/+16
* configure.in: Don't define SKIP_ZEROES. * configure: Regenerate. * objdump.c (disassemble_data): Set skip_zeroes and skip_zeroes_at_end in disasm_info to defaults. (DEFAULT_SKIP_ZEROES): Rename from SKIP_ZEROES and always define. (DEFAULT_SKIP_ZEROES_AT_END): Rename from SKIP_ZEROES_AT_END and always define. (disassemble_bytes): Use skip_zeroes and skip_zeroes_at_end from objdump_disasm_info. include/: * dis-asm.h (struct disassemble_info): Add skip_zeroes and skip_zeroes_at_end. opcodes/: * disassemble.c (disassemble_init_for_target) <case bfd_arch_ia64>: Set skip_zeroes to 16. <case bfd_arch_tic4x>: Set skip_zeroes to 32.
2004-12-232004-12-23 Tomer Levi <Tomer.Levi@nsc.com>Tomer Levi2-2/+6
* crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
2004-12-14Added printing of symbols on AVR disasmSvein Seldal1-2/+2
2004-12-14Added printing of symbols on AVR disasmSvein Seldal2-17/+30
2004-12-052004-12-05 Tomer Levi <Tomer.Levi@nsc.com>Tomer Levi1-0/+4
* crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
2004-12-052004-12-05 Tomer Levi <Tomer.Levi@nsc.com>Tomer Levi1-14/+17
* crx-dis.c: Use 'info->print_address_func' for address printing.
2004-11-292004-11-29 Tomer Levi <Tomer.Levi@nsc.com>Tomer Levi3-86/+102
* crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed. (no_op_insn): Initialize array with instructions that have no operands. * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
2004-11-29* arm-dis.c: Correct top-level comment.Richard Earnshaw2-1/+5
2004-11-27Tweak last entry.Richard Earnshaw1-1/+2
2004-11-27* arm-opc.h (arm_opcode, thumb_opcode): Add extra field for theRichard Earnshaw5-707/+722
architecuture defining the insn. (arm_opcodes, thumb_opcodes): Delete. Move to ... * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Also include opcode/arm.h. * Makefile.am (arm-dis.lo): Update dependency list. * Makefile.in: Regenerate.
2004-11-22* opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to reflect theNick Clifton2-0/+6
change to the short immediate syntax. * gas/arc/ld.s: Add check of load of a long immediate. * gas/arc/ld.d: Add expected disassembly.
2004-11-19 * or32-opc.c (debug): Warning fix.Alan Modra3-4/+6
* po/POTFILES.in: Regenerate.
2004-11-19 * maxq-dis.c: Formatting.Alan Modra2-9/+14
(print_insn): Warning fix.
2004-11-17bfd/Daniel Jacobowitz2-10/+21
* elf32-arm.c (PLT_THUMB_STUB_SIZE): Define. (elf32_arm_plt_thumb_stub): New. (struct elf32_arm_link_hash_entry): Add plt_thumb_refcount and plt_got_offset. (elf32_arm_link_hash_traverse): Fix typo. (elf32_arm_link_hash_table): Add obfd. (elf32_arm_link_hash_newfunc): Initialize new fields. (elf32_arm_copy_indirect_symbol): Copy plt_thumb_refcount. (elf32_arm_link_hash_table_create): Initialize obfd. (record_arm_to_thumb_glue): Mark the glue as a local ARM function. (record_thumb_to_arm_glue): Mark the glue as a local Thumb function. (bfd_elf32_arm_get_bfd_for_interworking): Verify that the interworking BFD is not dynamic. (bfd_elf32_arm_process_before_allocation): Handle R_ARM_PLT32. Do not emit glue for PLT references. (elf32_arm_final_link_relocate): Handle Thumb functions. Do not emit glue for PLT references. Support the Thumb PLT prefix. (elf32_arm_gc_sweep_hook): Handle R_ARM_THM_PC22 and plt_thumb_refcount. (elf32_arm_check_relocs): Likewise. (elf32_arm_adjust_dynamic_symbol): Handle Thumb functions and plt_thumb_refcount. (allocate_dynrelocs): Handle Thumb PLT references. (elf32_arm_finish_dynamic_symbol): Likewise. (elf32_arm_symbol_processing): New function. (elf_backend_symbol_processing): Define. opcodes/ * arm-dis.c (WORD_ADDRESS): Define. (print_insn): Use it. Correct big-endian end-of-section handling. gas/testsuite/ * gas/arm/mapping.d: Expect F markers for Thumb code. * gas/arm/unwind.d: Update big-endian pattern. ld/ * emultempl/armelf.em (arm_elf_set_bfd_for_interworking): Don't use a dynamic object for stubs. ld/testsuite/ * ld-arm/mixed-app.d, ld-arm/mixed-app.r, ld-arm/mixed-app.s, ld-arm/mixed-app.sym, ld-arm/mixed-lib.d, ld-arm/mixed-lib.r, ld-arm/mixed-lib.s, ld-arm/mixed-lib.sym, ld-arm/arm-dyn.ld, ld-arm/arm-lib.ld: New files. * ld-arm/arm-app-abs32.d, ld-arm/arm-app-abs32.r, ld-arm/arm-app.d, ld-arm/arm-app.r, ld-arm/arm-lib-plt32.d, ld-arm/arm-lib-plt32.r, ld-arm/arm-lib.d, ld-arm/arm-lib.r, ld-arm/arm-static-app.d, ld-arm/arm-static-app.r: Update for big-endian. * ld-arm/arm-elf.exp: Run the new tests.
2004-11-09oops - omitted from previous deltaNick Clifton1-0/+13
2004-11-08Add support fpr MAXQ processorNick Clifton7-19/+752
2004-11-052004-11-05 Tomer Levi <Tomer.Levi@nsc.com>Tomer Levi3-4/+10
* crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register mode. * crx-dis.c: Likewise.
2004-11-04 Generally, handle CRISv32.Hans-Peter Nilsson3-173/+874
* cris-dis.c (TRACE_CASE): Define as (disdata->trace_case). (struct cris_disasm_data): New type. (format_reg, format_hex, cris_constraint, print_flags) (get_opcode_entry): Add struct cris_disasm_data * parameter. All callers changed. (format_sup_reg, print_insn_crisv32_with_register_prefix) (print_insn_crisv32_without_register_prefix) (print_insn_crisv10_v32_with_register_prefix) (print_insn_crisv10_v32_without_register_prefix) (cris_parse_disassembler_options): New functions. (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family parameter. All callers changed. (get_opcode_entry): Call malloc, not xmalloc. Return NULL on failure. (cris_constraint) <case 'Y', 'U'>: New cases. (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes for constraint 'n'. (print_with_operands) <case 'Y'>: New case. (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'> <case 'N', 'Y', 'Q'>: New cases. (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32. (print_insn_cris_with_register_prefix) (print_insn_cris_without_register_prefix): Call cris_parse_disassembler_options. * cris-opc.c (cris_spec_regs): Mention that this table isn't used for CRISv32 and the size of immediate operands. New v32-only entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10. Change brp to be v3..v10. (cris_support_regs): New vector. (cris_opcodes): Update head comment. New format characters '[', ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'. Add new opcodes for v32 and adjust existing opcodes to accommodate differences to earlier variants. (cris_cond15s): New vector.
2004-11-04gas/Jan Beulich2-71/+201
2004-11-04 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (set_intel_syntax): Allow % in symbol names when intel syntax and no register prefix, allow $ in symbol names when intel syntax. (set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX. (intel_float_operand): Add fourth return value indicating math control operations. Make classification more precise. (md_assemble): Complain if memory operand of mov[sz]x has no size specified. (parse_insn): Translate word operands to floating point instructions operating on integers as well as control instructions to short ones as expected by AT&T syntax. Translate 'd' suffix to short one only for floating point instructions operating on non-integer operands. (match_template): Remove fldcw special case. Adjust q-suffix handling to permit it on fild/fistp/fisttp in AT&T mode. (process_suffix): Don't guess DefaultSize insns' suffix from stackop_size for certain floating point control instructions. Guess suffix for branch and [ls][gi]dt based on flag_code. Split error messages for Intel and AT&T syntax, and make the condition more strict for the former. Adjust suppressing of generation of operand size overrides. (intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE, OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add more error checking. * config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines. gas/testsuite/ 2004-11-04 Jan Beulich <jbeulich@novell.com> * gas/i386/i386.exp: Execute new tests intelbad and intelok. * gas/i386/intelbad.[sl]: New test to check for various things not permitted in Intel mode. * gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d: Adjust for change to segment register store. * gas/i386/intelok.[sd]: New test to check various Intel mode specific things get handled correctly. * gas/i386/x86_64.[sd]: Remove unsupported constructs referring to 'high' and 'low' parts of an operand, which the parser previously accepted while neither telling that it's not supported nor that it ignored the remainder of the line following these supposed keywords. include/opcode/ 2004-11-04 Jan Beulich <jbeulich@novell.com> * i386.h (sldx_Suf): Remove. (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. (q_FP): Define, implying no REX64. (x_FP, sl_FP): Imply FloatMF. (i386_optab): Split reg and mem forms of moving from segment registers so that the memory forms can ignore the 16-/32-bit operand size distinction. Adjust a few others for Intel mode. Remove *FP uses from all non-floating-point instructions. Unite 32- and 64-bit forms of movsx, movzx, and movd. Adjust floating point operations for the above changes to the *FP macros. Add DefaultSize to floating point control insns operating on larger memory ranges. Remove left over comments hinting at certain insns being Intel-syntax ones where the ones actually meant are already gone. opcodes/ 2004-11-04 Jan Beulich <jbeulich@novell.com> * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define. (indirEb): Remove. (Mp): Use f_mode rather than none at all. (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode replaces what previously was x_mode; x_mode now means 128-bit SSE operands. (dis386): Make far jumps and calls have an 'l' prefix only in AT&T mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq. pinsrw's second operand is Edqw. (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt, fldenv, frstor, fsave, fstenv all should also have suffixes in Intel mode when an operand size override is present or always suffixing. More instructions will need to be added to this group. (putop): Handle new macro chars 'C' (short/long suffix selector), 'I' (Intel mode override for following macro char), and 'J' (for adding the 'l' prefix to far branches in AT&T mode). When an alternative was specified in the template, honor macro character when specified for Intel mode. (OP_E): Handle new *_mode values. Correct pointer specifications for memory operands. Consolidate output of index register. (OP_G): Handle new *_mode values. (OP_I): Handle const_1_mode. (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate respective opcode prefix bits have been consumed. (OP_EM, OP_EX): Provide some default handling for generating pointer specifications.
2004-10-282004-10-28 Tomer Levi <Tomer.Levi@nsc.com>Tomer Levi1-0/+5
* crx-opc.c (REV_COP_INST): New macro, reverse operand order of COP_INST macro.
2004-10-282004-10-27 Tomer Levi <Tomer.Levi@nsc.com>Tomer Levi1-9/+13
* crx-opc.c (REV_COP_INST): New macro, reverse operand order of COP_INST macro.
2004-10-272004-10-27 Tomer Levi <Tomer.Levi@nsc.com>Tomer Levi1-0/+12
* crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE. (getregliststring): Support HI/LO and user registers. * crx-opc.c (crx_instruction): Update data structure according to the rearrangement done in CRX opcode header file. (crx_regtab): Likewise. (crx_optab): Likewise. (crx_instruction): Reorder load/stor instructions, remove unsupported formats. support new Co-Processor instruction 'cpi'.
2004-10-27* crx-opc.c (crx_instruction): Update data structure according to the ↵Tomer Levi1-232/+237
rearrangement done in CRX opcode header file. (crx_regtab): Likewise. (crx_optab): Likewise. (crx_instruction): Reorder load/stor instructions, remove unsupported formats. support new Co-Processor instruction 'cpi'.
generated by cgit v1.1 at 2024-11-20 14:29:22 +0000