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2024-01-05RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvliJin Ma1-0/+22
Since the particularity of "th.vsetvli" was not taken into account in the initial support patches for XTheadVector, the program operation failed due to instruction coding errors. According to T-Head SPEC ([1]), the "vsetvl" in the XTheadVector extension consists of SEW, LMUL and EDIV, which is quite different from the "V" extension. Therefore, we cannot simply reuse the processing of vsetvl in V extension. We have set up tens of thousands of test cases to ensure that no further encoding issues are there, and and execute all compiled test files on real HW and make sure they don't trigger SIGILL. Ref: [1] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add handling for th.vsetvli. (my_getThVsetvliExpression): New function. (riscv_ip): Likewise. * testsuite/gas/riscv/x-thead-vector.d: Likewise. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv.h (OP_MASK_XTHEADVLMUL): New macro. (OP_SH_XTHEADVLMUL): Likewise. (OP_MASK_XTHEADVSEW): Likewise. (OP_SH_XTHEADVSEW): Likewise. (OP_MASK_XTHEADVEDIV): Likewise. (OP_SH_XTHEADVEDIV): Likewise. (OP_MASK_XTHEADVTYPE_RES): Likewise. (OP_SH_XTHEADVTYPE_RES): Likewise. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Likewise. * riscv-opc.c: Likewise.
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
2023-12-01RISC-V: Make riscv_is_mapping_symbol stricterPatrick O'Neill1-3/+1
riscv_is_mapping_symbol currently accepts any symbol that starts with $x or $d. This patch makes the check more strict, requiring exactly $x, $d, or $xrv. It also makes use of this stricter mapping in riscv_is_valid_mapping_symbol. ChangeLog: * bfd/cpu-riscv.c (riscv_elf_is_mapping_symbols): Match only strings that are exactly $x, $d, or $xrv. * opcodes/riscv-dis.c (riscv_is_valid_mapping_symbol): Use riscv_elf_is_mapping_symbols. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu1-0/+27
SiFive has define as set of flexible instruction for extending vector coprocessor, it able to encoding opcode like .insn but with predefined format. List of instructions: sf.vc.x sf.vc.i sf.vc.vv sf.vc.xv sf.vc.iv sf.vc.fv sf.vc.vvv sf.vc.xvv sf.vc.ivv sf.vc.fvv sf.vc.vvw sf.vc.xvw sf.vc.ivw sf.vc.fvw sf.vc.v.x sf.vc.v.i sf.vc.v.vv sf.vc.v.xv sf.vc.v.iv sf.vc.v.fv sf.vc.v.vvv sf.vc.v.xvv sf.vc.v.ivv sf.vc.v.fvv sf.vc.v.vvw sf.vc.v.xvw sf.vc.v.ivw sf.vc.v.fvw Spec of Xsfvcp https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software Co-authored-by: Hau Hsu <hau.hsu@sifive.com> Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
2023-11-30RISC-V: Avoid updating state until symbol is foundPatrick O'Neill1-12/+31
Currently objdump gets and updates the map state once per symbol. Updating the state (partiularly riscv_parse_subset) is expensive and grows quadratically since we iterate over all symbols. By deferring this until once we've found the symbol of interest, we can reduce the time to dump a 4k insn file of .norvc and .rvc insns from ~47 seconds to ~0.13 seconds. opcodes/ChangeLog: * riscv-dis.c (riscv_get_map_state): Remove state updating logic and rename to riscv_is_valid_mapping_symbol. (riscv_update_map_state): Add state updating logic to seperate function. (riscv_search_mapping_symbol): Use new riscv_update_map_state. (riscv_data_length): Ditto. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-11-24RISC-V: disallow x0 with certain macro-insnsJan Beulich1-0/+3
While for some of the macro insns using x0 is kind of okay, as they would merely resolve to a sequence of hint insns (and hence not cause misbehavior at runtime), several of them have the degenerate AUIPC followed by a load, store, or branch using other than the designated symbol as address and hence causing runtime issues. Refuse to assemble those, leveraging that the matching function so far wasn't really used for macro insns: NULL is now allowed, indicating a match (which imo is preferable over converting match_never() to match_always()), while other matching functions now (also) used for macro insns need to avoid calling match_opcode(). Note that for LA the restriction is slightly too strict: In non-PIC mode using x0 would be okay-ish as per above (as it's just LLA there). Yet libopcodes doesn't know what mode gas is presently assembling for, so we want to err on the safe side. Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-11-23RISC-V: Add CSRs for T-Head VECTOR vendor extensionJin Ma1-2/+12
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the CSRs for XTheadVector. Because of the conflict between encoding and teh 'V' extension, it is implemented by alias. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add the class for the CSRs of the "XTheadVector" extension. (riscv_csr_address): Likewise. * testsuite/gas/riscv/x-thead-vector-csr-warn.d: New test. * testsuite/gas/riscv/x-thead-vector-csr-warn.l: New test. * testsuite/gas/riscv/x-thead-vector-csr.d: New test. * testsuite/gas/riscv/x-thead-vector-csr.s: New test. include/ChangeLog: * opcode/riscv-opc.h (DECLARE_CSR_ALIAS): Likewise. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Prefix the CSRs disassembly with 'th'.
2023-11-07RISC-V: Add support for XCValu extension in CV32E40PMary Bennett1-0/+4
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Added the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Noted XCValu as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-alu-boundaries.d: New test. * testsuite/gas/riscv/cv-alu-boundaries.l: New test. * testsuite/gas/riscv/cv-alu-boundaries.s: New test. * testsuite/gas/riscv/cv-alu-fail-march.d: New test. * testsuite/gas/riscv/cv-alu-fail-march.l: New test. * testsuite/gas/riscv/cv-alu-fail-march.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test. * testsuite/gas/riscv/cv-alu-insns.d: New test. * testsuite/gas/riscv/cv-alu-insns.s: New test. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Disassemble xcb operand. * riscv-opc.c: Defined the MASK and added XCValu instructions. include/ChangeLog: * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros for XCValu. * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros for XCValu. (enum riscv_insn_class): Added the XCValu instruction class.
2023-11-07RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett1-0/+11
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Added the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Noted XCVmac as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-mac-fail-march.d: New test. * testsuite/gas/riscv/cv-mac-fail-march.l: New test. * testsuite/gas/riscv/cv-mac-fail-march.s: New test. * testsuite/gas/riscv/cv-mac-fail-operand.d: New test. * testsuite/gas/riscv/cv-mac-fail-operand.l: New test. * testsuite/gas/riscv/cv-mac-fail-operand.s: New test. * testsuite/gas/riscv/cv-mac-insns.d: New test. * testsuite/gas/riscv/cv-mac-insns.s: New test. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Disassemble information with the EXTRACT macro implemented. * riscv-opc.c: Defined the MASK and added XCVmac instructions. include/ChangeLog: * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros for XCVmac. * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros for uimm. (enum riscv_insn_class): Added the XCVmac instruction class.
2023-10-13RISC-V: Add support for numbered ISA mapping stringsJoseph Faulls1-1/+15
The elf psabi allows for mapping symbols to be of the form $x<ISA>.<any> opcodes/ * riscv-dis.c (riscv_get_map_state): allow mapping symbol to be suffixed by a unique identifier .<any>
2023-09-07RISC-V: Clarify the naming rules of vendor operands.Nelson Chu1-81/+86
The vendor operands should be named starting with `X', and preferably the second letter (or multiple following letters) is enough to differentiate them from other vendors. Therefore, added letter `t' after `X' for t-head operands, to differentiate from future different vendor's operands. bfd/ * elfxx-riscv.c (riscv_supported_vendor_x_ext): Removed the vendor document link since it should already be recorded in the gas/doc/c-riscv.texi. gas/ * config/tc-riscv.c (validate_riscv_insn): Added `t' after `X' for t-head operands. Minor updates for indents and comments. (riscv_ip): Likewise. * doc/c-riscv.texi: Minor updates. opcodes/ * riscv-dis.c (print_insn_args): Added `t' after `X' for t-head operands. Minor updates for indents and comments. * riscv-opc.c (riscv_opcode): Likewise.
2023-08-15RISC-V: remove indirection from register tablesJan Beulich1-6/+6
The longest register name is 4 characters (plus a nul one), so using a 4- or 8-byte pointer to get at it is neither space nor time efficient. Embed the names right into the array. For PIE this also reduces the number of base relocations in the final image. To avoid old gcc, when generating 32-bit code, bogusly warning about bounds being exceeded in the code processing Cs/Cw, Ct/Cx, and CD, an adjustment to EXTRACT_BITS() is needed: This macro shouldn't supply a 64-bit value, and it also doesn't need to - all operand fields to date are far more narrow than 32 bits. This in turn allows dropping a number of casts elsewhere.
2023-08-02Revert "2.41 Release sources"Sam James1-1/+15
This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-15/+1
2023-07-28Fix typo in riscv-dis.c commentTsukasa OI1-1/+1
Don't go "past" the start of the section.
2023-07-18RISC-V: Supports Zcb extension.Jiawei1-0/+14
This patch support Zcb extension, contains new compressed instructions, some instructions depend on other existed extension, like 'zba', 'zbb' and 'zmmul'. Zcb also imply Zca extension to enable the compressing features. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcb.d: New test. * testsuite/gas/riscv/zcb.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_C_LBU): New opcode. (MASK_C_LBU): New mask. (MATCH_C_LHU): New opcode. (MASK_C_LHU): New mask. (MATCH_C_LH): New opcode. (MASK_C_LH): New mask. (MATCH_C_SB): New opcode. (MASK_C_SB): New mask. (MATCH_C_SH): New opcode. (MASK_C_SH): New mask. (MATCH_C_ZEXT_B): New opcode. (MASK_C_ZEXT_B): New mask. (MATCH_C_SEXT_B): New opcode. (MASK_C_SEXT_B): New mask. (MATCH_C_ZEXT_H): New opcode. (MASK_C_ZEXT_H): New mask. (MATCH_C_SEXT_H): New opcode. (MASK_C_SEXT_H): New mask. (MATCH_C_ZEXT_W): New opcode. (MASK_C_ZEXT_W): New mask. (MATCH_C_NOT): New opcode. (MASK_C_NOT): New mask. (MATCH_C_MUL): New opcode. (MASK_C_MUL): New mask. (DECLARE_INSN): New opcode. * opcode/riscv.h (EXTRACT_ZCB_BYTE_UIMM): New inline func. (EXTRACT_ZCB_HALFWORD_UIMM): Ditto. (ENCODE_ZCB_BYTE_UIMM): Ditto. (ENCODE_ZCB_HALFWORD_UIMM): Ditto. (VALID_ZCB_BYTE_UIMM): Ditto. (VALID_ZCB_HALFWORD_UIMM): Ditto. (enum riscv_insn_class): New extension class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): New operators. * riscv-opc.c: New instructions.
2023-07-01RISC-V: Add support for the Zvbb ISA extensionChristoph Müllner1-0/+4
Zvbb is part of the vector crypto extensions. This extension adds the following instructions: - vandn.[vv,vx] - vbrev.v - vbrev8.v - vrev8.v - vclz.v - vctz.v - vcpop.v - vrol.[vv,vx] - vror.[vv,vx,vi] - vwsll.[vv,vx,vi] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvbb. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add 'l' as new format string directive. (riscv_ip): Likewise. * testsuite/gas/riscv/zvbb.d: New test. * testsuite/gas/riscv/zvbb.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VANDN_VV): New. (MASK_VANDN_VV): New. (MATCH_VANDN_VX): New. (MASK_VANDN_VX): New. (MATCH_VBREV8_V): New. (MASK_VBREV8_V): New. (MATCH_VBREV_V): New. (MASK_VBREV_V): New. (MATCH_VCLZ_V): New. (MASK_VCLZ_V): New. (MATCH_VCPOP_V): New. (MASK_VCPOP_V): New. (MATCH_VCTZ_V): New. (MASK_VCTZ_V): New. (MATCH_VREV8_V): New. (MASK_VREV8_V): New. (MATCH_VROL_VV): New. (MASK_VROL_VV): New. (MATCH_VROL_VX): New. (MASK_VROL_VX): New. (MATCH_VROR_VI): New. (MASK_VROR_VI): New. (MATCH_VROR_VV): New. (MASK_VROR_VV): New. (MATCH_VROR_VX): New. (MASK_VROR_VX): New. (MATCH_VWSLL_VI): New. (MASK_VWSLL_VI): New. (MATCH_VWSLL_VV): New. (MASK_VWSLL_VV): New. (MATCH_VWSLL_VX): New. (MASK_VWSLL_VX): New. (DECLARE_INSN): New. * opcode/riscv.h (EXTRACT_RVV_VI_UIMM6): New. (ENCODE_RVV_VI_UIMM6): New. (enum riscv_insn_class): Add instruction class for Zvbb. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add 'l' as new format string directive. * riscv-opc.c: Add Zvbb instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-06-30RISC-V: Add support for the Zfa extensionChristoph Müllner1-0/+16
This patch adds support for the RISC-V Zfa extension, which introduces additional floating-point instructions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Modular Convert-to-Integer) * fmv* to access high bits of FP registers in case XLEN < FLEN * fleq/fltq (quiet comparison instructions) Zfa defines its instructions in combination with the following extensions: * single-precision floating-point (F) * double-precision floating-point (D) * quad-precision floating-point (Q) * half-precision floating-point (Zfh) This patch is based on an earlier version from Tsukasa OI: https://sourceware.org/pipermail/binutils/2022-September/122939.html Most significant change to that commit is the switch from the rs1-field value to the actual floating-point value in the last operand of the fli* instructions. Everything that strtof() can parse is accepted and the '%a' printf specifier is used to output hex floating-point literals in the disassembly. The Zfa specification is frozen (and has passed public review). It is available as a chapter in "The RISC-V Instruction Set Manual: Volume 1": https://github.com/riscv/riscv-isa-manual/releases bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for 'Zfa' extension. (riscv_multi_subset_supports_ext): Likewise. (riscv_implicit_subsets): Add 'Zfa' -> 'F' dependency. gas/ChangeLog: * config/tc-riscv.c (flt_lookup): New helper to lookup a float value in an array. (validate_riscv_insn): Add 'Wfv' as new format string directive. (riscv_ip): Likewise. * doc/c-riscv.texi: Add floating-point chapter and describe limiations of the Zfa FP literal parsing. * testsuite/gas/riscv/zfa-32.d: New test. * testsuite/gas/riscv/zfa-32.s: New test. * testsuite/gas/riscv/zfa-64.d: New test. * testsuite/gas/riscv/zfa-64.s: New test. * testsuite/gas/riscv/zfa-fail.d: New test. * testsuite/gas/riscv/zfa-fail.l: New test. * testsuite/gas/riscv/zfa-fail.s: New test. * testsuite/gas/riscv/zfa.d: New test. * testsuite/gas/riscv/zfa.s: New test. * testsuite/gas/riscv/zfa.s: New test. * opcode/riscv-opc.h (MATCH_FLI_H): New. (MASK_FLI_H): New. (MATCH_FMINM_H): New. (MASK_FMINM_H): New. (MATCH_FMAXM_H): New. (MASK_FMAXM_H): New. (MATCH_FROUND_H): New. (MASK_FROUND_H): New. (MATCH_FROUNDNX_H): New. (MASK_FROUNDNX_H): New. (MATCH_FLTQ_H): New. (MASK_FLTQ_H): New. (MATCH_FLEQ_H): New. (MASK_FLEQ_H): New. (MATCH_FLI_S): New. (MASK_FLI_S): New. (MATCH_FMINM_S): New. (MASK_FMINM_S): New. (MATCH_FMAXM_S): New. (MASK_FMAXM_S): New. (MATCH_FROUND_S): New. (MASK_FROUND_S): New. (MATCH_FROUNDNX_S): New. (MASK_FROUNDNX_S): New. (MATCH_FLTQ_S): New. (MASK_FLTQ_S): New. (MATCH_FLEQ_S): New. (MASK_FLEQ_S): New. (MATCH_FLI_D): New. (MASK_FLI_D): New. (MATCH_FMINM_D): New. (MASK_FMINM_D): New. (MATCH_FMAXM_D): New. (MASK_FMAXM_D): New. (MATCH_FROUND_D): New. (MASK_FROUND_D): New. (MATCH_FROUNDNX_D): New. (MASK_FROUNDNX_D): New. (MATCH_FLTQ_D): New. (MASK_FLTQ_D): New. (MATCH_FLEQ_D): New. (MASK_FLEQ_D): New. (MATCH_FLI_Q): New. (MASK_FLI_Q): New. (MATCH_FMINM_Q): New. (MASK_FMINM_Q): New. (MATCH_FMAXM_Q): New. (MASK_FMAXM_Q): New. (MATCH_FROUND_Q): New. (MASK_FROUND_Q): New. (MATCH_FROUNDNX_Q): New. (MASK_FROUNDNX_Q): New. (MATCH_FLTQ_Q): New. (MASK_FLTQ_Q): New. (MATCH_FLEQ_Q): New. (MASK_FLEQ_Q): New. (MATCH_FCVTMOD_W_D): New. (MASK_FCVTMOD_W_D): New. (MATCH_FMVH_X_D): New. (MASK_FMVH_X_D): New. (MATCH_FMVH_X_Q): New. (MASK_FMVH_X_Q): New. (MATCH_FMVP_D_X): New. (MASK_FMVP_D_X): New. (MATCH_FMVP_Q_X): New. (MASK_FMVP_Q_X): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction classes for the Zfa extension. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add support for new format string directive 'Wfv'. * riscv-opc.c: Add Zfa instructions. Co-Developed-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Co-Developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-05-19RISC-V: Minor improvements for dis-assembler.Nelson Chu1-21/+37
* Extract all private_data initializations into riscv_init_disasm_info, which called from print_insn_riscv rather than riscv_disassemble_insn. * The disassemble_free_target seems like the right place to release all target private_data, also including the internal data structures, like riscv_subsets. Therefore, add a new function, disassemble_free_riscv, to release them for safe. opcodes/ * disassemble.c (disassemble_free_target): Called disassemble_free_riscv for riscv to release private_data and internal data structures. * disassemble.h: Added extern disassemble_free_riscv. * riscv-dis.c (riscv_init_disasm_info): New function, used to init riscv_private_data. (riscv_disassemble_insn): Moved riscv_private_data initializations into riscv_init_disasm_info. (print_insn_riscv): Called riscv_init_disasm_info to init riscv_private_data once time. (disassemble_free_riscv): New function, used to free the internal data structures, like riscv_subsets.
2023-04-18RISC-V: Cache the latest mapping symbol and its boundary.Kito Cheng1-0/+43
This issue was reported from https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1188 Current flow: 1) Scan any mapping symbol less than this instruciton. 2) If not found, did a backward search. The flow seems not big issue, let run an example here: $x: 0x0 a <--- Found at step 1 0x4 b <--- Not found in step 1, but found at step 2 0x8 c <--- Not found in step 1, but found at step 2 $d 0x12 .word 1234 <-- Found at step 1 The instruciton didn't have the same address with mapping symbol will still did backward search again and again. So the new flow is: 1) Use the last mapping symbol status if the address is still within the range of the current mapping symbol. 2) Scan any mapping symbol less than this instruciton. 3) If not found, did a backward search. 4) If a proper mapping symbol is found in either step 2 or 3, find its boundary, and cache that. Use the same example to run the new flow again: $x: 0x0 a <--- Found at step 2, the boundary is 0x12 0x4 b <--- Cache hit at step 1, within the boundary. 0x8 c <--- Cache hit at step 1, within the boundary. $d 0x12 .word 1234 <-- Found at step 2, the boundary is the end of section. The disassemble time of the test cases has been reduced from ~20 minutes to ~4 seconds. opcode/ChangeLog PR 30282 * riscv-dis.c (last_map_symbol_boundary): New. (last_map_state): New. (last_map_section): New. (riscv_search_mapping_symbol): Cache the result of latest mapping symbol.
2023-03-31RISC-V: Allocate "various" operand typeTsukasa OI1-5/+21
This commit intends to move operands that require very special handling or operand types that are so minor (e.g. only useful on a few instructions) under "W". I also intend this "W" to be "temporary" operand storage until we can find good two character (or less) operand type. In this commit, prefetch offset operand "f" for 'Zicbop' extension is moved to "Wif" because of its special handling (and allocating single character "f" for this operand type seemed too much). Current expected allocation guideline is as follows: 1. 'W' 2. The most closely related single-letter extension in lowercase (strongly recommended but not mandatory) 3. Identify operand type The author currently plans to allocate following three-character operand types (for operands including instructions from unratified extensions). 1. "Wif" ('Zicbop': fetch offset) 2. "Wfv" (unratified 'Zfa': value operand from FLI.[HSDQ] instructions) 3. "Wfm" / "WfM" 'Zfh', 'F', 'D', 'Q': rounding modes "m" with special handling solely for widening conversion instructions. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn, riscv_ip): Move from "f" to "Wif". opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Move from "f" to "Wif". * riscv-opc.c (riscv_opcodes): Reflect new operand type.
2023-03-21RISC-V: Fix disassemble fetch fail return value.Jiawei1-2/+2
This bug reported in https://sourceware.org/bugzilla/show_bug.cgi?id=30184 And discussed in https://sourceware.org/pipermail/binutils/2023-February/126213.html We also checked the implementation of return value in arm and mips. So this patch changes the return value to -1, that can fix bugs and maintain consistency with other architectures. opcodes/ChangeLog: * riscv-dis.c (print_insn_riscv):Change the return value.
2023-02-03RISC-V: don't disassemble unrecognized insns as .byteJan Beulich1-30/+20
Insn width granularity being 16 bits, producing byte granular output isn't very useful. With there being a way to specific otherwise unknown insns to the assembler, use that same representation (to be precise: its <length>,<encoding> flavor) for disassembly.
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2022-11-28RISC-V: Better support for long instructions (disassembler)Tsukasa OI1-5/+9
Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit instructions with .insn") tried to start supporting long instructions but it was insufficient. On the disassembler, correct ".byte" output was limited to the first 64-bits of an instruction. After that, zeroes are incorrectly printed. Note that, it only happens on ".byte" output (instruction part) and not on hexdump (data) part. For example, before this commit, hexdump and ".byte" produces different values: Assembly: .insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f objdump output example (before the fix): 10: 607f 33cc 55aa cdef .byte 0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 18: 89ab 4567 0123 3210 20: 7654 ba98 fedc Note that, after 0xcd (after first 64-bits of the target instruction), all ".byte" values are incorrectly printed as zero while hexdump prints correct instruction bits. To resolve this, this commit adds "packet" argument to support dumping instructions longer than 64-bits (to print correct instruction bits on ".byte"). This commit will be tested on the separate commit. Assembly: .insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f objdump output example (after the fix): 10: 607f 33cc 55aa cdef .byte 0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe 18: 89ab 4567 0123 3210 20: 7654 ba98 fedc opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Print unknown instruction using the new argument packet. (riscv_disassemble_data): Add unused argument packet. (print_insn_riscv): Pass packet to the disassemble function.
2022-10-28RISC-V: Output mapping symbols with ISA string.Nelson Chu1-0/+9
RISC-V Psabi pr196, https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/196 bfd/ * elfxx-riscv.c (riscv_release_subset_list): Free arch_str if needed. (riscv_copy_subset_list): Copy arch_str as well. * elfxx-riscv.h (riscv_subset_list_t): Store arch_str for each subset list. gas/ * config/tc-riscv.c (riscv_reset_subsets_list_arch_str): Update the architecture string in the subset_list. (riscv_set_arch): Call riscv_reset_subsets_list_arch_str after parsing new architecture string. (s_riscv_option): Likewise. (need_arch_map_symbol): New boolean, used to indicate if .option directives do affect instructions. (make_mapping_symbol): New boolean parameter reset_seg_arch_str. Need to generate $x+arch for MAP_INSN, and then store it into tc_segment_info_data if reset_seg_arch_str is true. (riscv_mapping_state): Decide if we need to add $x+arch for MAP_INSN. For now, only add $x+arch if the architecture strings in subset list and segment are different. Besides, always add $x+arch at the start of section, and do not add $x+arch for code alignment, since rvc for alignment can be judged from addend of R_RISCV_ALIGN. (riscv_remove_mapping_symbol): If current and previous mapping symbol have same value, then remove the current $x only if the previous is $x+arch; Otherwise, always remove previous. (riscv_add_odd_padding_symbol): Updated. (riscv_check_mapping_symbols): Don't need to add any $x+arch if need_arch_map_symbol is false, so changed them to $x. (riscv_frag_align_code): Updated since riscv_mapping_state is changed. (riscv_init_frag): Likewise. (s_riscv_insn): Likewise. (riscv_elf_final_processing): Call riscv_release_subset_list to release subset_list of riscv_rps_as, rather than only release arch_str in the riscv_write_out_attrs. (riscv_write_out_attrs): No need to call riscv_arch_str, just get arch_str from subset_list of riscv_rps_as. * config/tc-riscv.h (riscv_segment_info_type): Record current $x+arch mapping symbol of each segment. * testsuite/gas/riscv/mapping-0*: Merged and replaced by mapping.s. * testsuite/gas/riscv/mapping.s: New testcase, to test most of the cases in one file. * testsuite/gas/riscv/mapping-symbols.d: Likewise. * testsuite/gas/riscv/mapping-dis.d: Likewise. * testsuite/gas/riscv/mapping-non-arch.s: New testcase for the case that does need any $x+arch. * testsuite/gas/riscv/mapping-non-arch.d: Likewise. * testsuite/gas/riscv/option-arch-01a.d: Updated. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Set riscv_fpr_names back to riscv_fpr_names_abi or riscv_fpr_names_numeric when zfinx is disabled for some specfic code region. (riscv_get_map_state): Recognized mapping symbols $x+arch, and then reset the architecture string once the ISA is different.
2022-10-14opcodes/riscv-dis.c: Remove last_map_stateTsukasa OI1-3/+0
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. This commit removes unused variable last_map_state (set by the print_insn_riscv function but not read anywhere else). opcodes/ChangeLog: * riscv-dis.c (last_map_state): Remove. (print_insn_riscv): Remove setting last_map_state.
2022-10-14opcodes/riscv-dis.c: Make XLEN variable staticTsukasa OI1-1/+1
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. Since xlen variable is not (and should not) used outside riscv-dis.c, this commit makes this variable static. opcodes/ChangeLog: * riscv-dis.c (xlen): Make this variable static.
2022-10-14opcodes/riscv-dis.c: Use bool type whenever possibleTsukasa OI1-5/+5
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. This commit replaces uses of int with bool whenever possible. opcodes/ChangeLog: * riscv-dis.c (no_aliases) Change type to bool. (set_default_riscv_dis_options): Use boolean. (parse_riscv_dis_option_without_args): Likewise. (riscv_disassemble_insn): Use boolean keywords.
2022-10-14opcodes/riscv-dis.c: Tidying with spacingTsukasa OI1-1/+1
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. This commit takes care of improper spacing for code clarity. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Tidying with spacing.
2022-10-14opcodes/riscv-dis.c: Tidying with comments/clarityTsukasa OI1-4/+21
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. First, we need to clarify the roles of variables and code portions. opcodes/ChangeLog: * riscv-dis.c (xlen): Move before default_isa_spec. Add comment. (default_isa_spec, default_priv_spec): Add comment. (riscv_gpr_names, riscv_fpr_names): Likewise. (parse_riscv_dis_option_without_args): Likewise. (parse_riscv_dis_option, parse_riscv_dis_options): Likewise. (maybe_print_address): Likewise. (riscv_disassemble_insn): Fix comment about the Zfinx "extension". Add comment about the riscv_multi_subset_supports call.
2022-10-06RISC-V: Print XTheadMemPair literal as "immediate"Tsukasa OI1-1/+1
The operand type "Xl(...)" denotes that (...) is a literal. Specifically, they are intended to be a constant immediate value. This commit prints "Xl(...)" operand with dis_style_immediate style, not dis_style_text. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Use dis_style_immediate on the constant literal of the "Xl..." operand.
2022-10-06RISC-V: Fix T-Head immediate types on printingTsukasa OI1-4/+4
This commit fixes two minor typing-related issues for T-Head immediate operands. 1. A signed type must be specified when printing with %i. 2. unsigned/signed int is not portable enough for max 32-bit immediates. Instead, we should use unsigned/signed long. The format string is changed accordingly. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Fix T-Head immediate types on printing.
2022-10-06RISC-V: Print comma and tabs as the "text" styleTsukasa OI1-11/+20
On the RISC-V disassembler, some separators have non-text style when printed with another word with another style. This commit splits those, making sure that those comma and tabs are printed with the "text" style. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Split and print the comma as text. (riscv_disassemble_insn): Split and print tabs as text. (riscv_disassemble_data): Likewise.
2022-10-06RISC-V: Optimize riscv_disassemble_data printfTsukasa OI1-6/+4
This commit makes types of printf arguments on riscv_disassemble_data as small as possible (as long as we can preserve the portability) to reduce the cost of printf (especially on 32-bit host). opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_data): Use smallest possible type to printing data.
2022-10-06RISC-V: Fix printf argument types corresponding %xTsukasa OI1-7/+7
"%x" format specifier requires unsigned type, not int. This commit fixes this issue on the RISC-V disassembler. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Fix printf argument types where the format specifier is "%x".
2022-10-06RISC-V: Fix immediates to have "immediate" styleTsukasa OI1-5/+5
This commit fixes certain print calls on immediate operands to have dis_style_immediate. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Fix immediates to have "immediate" style. (riscv_disassemble_data): Likewise.
2022-10-04RISC-V: Fix buffer overflow on print_insn_riscvTsukasa OI1-1/+1
Because riscv_insn_length started to support instructions up to 176-bit, we need to increase packet buffer size to 176-bit in size. include/ChangeLog: * opcode/riscv.h (RISCV_MAX_INSN_LEN): Max instruction length for use in buffer size. opcodes/ChangeLog: * riscv-dis.c (print_insn_riscv): Increase buffer size for max 176-bit length instructions.
2022-10-04opcodes/riscv: style csr names as registersAndrew Burgess1-1/+2
While reviewing another patch I noticed that RISC-V CSR names are given the text style, not the register style. This patch fixes this mistake.
2022-09-30RISC-V: fix build after "Add support for arbitrary immediate encoding formats"Jan Beulich1-2/+2
Pre- and post-increment/decrement are side effects, the behavior of which is undefined when combined with passing an address of the accessed variable in the same function invocation. There's no need for the increments here - simply adding 1 achieves the intended effect without triggering compiler diagnostics (which are fatal with -Werror).
2022-09-22RISC-V: Add support for literal instruction argumentsChristoph Müllner1-0/+9
This patch introduces support for arbitrary literal instruction arguments, that are not encoded in the opcode. A typical use case for this feature would be an instruction that applies an implicit shift by a constant value on an immediate (that is a real operand). With this patch it is possible to make this shift visible in the dissasembly and support such artificial parameter as part of the asssembly code. Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner1-0/+34
This patch introduces support for arbitrary signed or unsigned immediate encoding formats. The formats have the form "XsN@S" and "XuN@S" with N being the number of bits and S the LSB position. For example an immediate field of 5 bytes that encodes a signed value and is stored in the bits 24-20 of the instruction word can use the format specifier "Xs5@20". Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Remove "b" operand type from disassemblerTsukasa OI1-1/+0
There are a few operand types not used by any RISC-V instructions. - Cx - Vf - Ve - [ - ] - b But most of them has a reasoning to keep them: - Cx : Same as "Ct" except it has a constraint to have rd == rs2 (similar to "Cw"). Although it hasn't used, its role is clear enough to implement a new instruction with this operand type. - Vf, Ve : Used by vector AMO instructions (not ratified and real instructions are not upstreamed yet). - [, ] : Unused tokenization symbols. Reserving them is not harmful and a vendor may use this symbol for special purposes. ... except "b". I could not have found any reference to this operand type except it works like the "s" operand type. Historically, it seems... it's just unused from the beginning. Its role is not clear either. On such cases, we should vacate this room for the new operand type with much clearer roles. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Remove 'b' operand type.
2022-09-06opcodes: Add non-enum disassembler optionsTsukasa OI1-0/+2
This is paired with "gdb: Add non-enum disassembler options". There is a portable mechanism for disassembler options and used on some architectures: - ARC - Arm - MIPS - PowerPC - RISC-V - S/390 However, it only supports following forms: - [NAME] - [NAME]=[ENUM_VALUE] Valid values for [ENUM_VALUE] must be predefined in disasm_option_arg_t.values. For instance, for -M cpu=[CPU] in ARC architecture, opcodes/arc-dis.c builds valid CPU model list from include/elf/arc-cpu.def. In this commit, it adds following format: - [NAME]=[ARBITRARY_VALUE] (cannot contain "," though) This is identified by NULL value of disasm_option_arg_t.values (normally, this is a non-NULL pointer to a NULL-terminated list). include/ChangeLog: * dis-asm.h (disasm_option_arg_t): Update comment of values to allow non-enum disassembler options. opcodes/ChangeLog: * riscv-dis.c (print_riscv_disassembler_options): Support non-enum disassembler options on printing disassembler help. * arc-dis.c (print_arc_disassembler_options): Likewise. * mips-dis.c (print_mips_disassembler_options): Likewise.
2022-09-02RISC-V: Print highest address (-1) on the disassemblerTsukasa OI1-6/+14
This patch makes possible to print the highest address (-1) and the addresses related to gp which value is -1. This is particularly useful if the highest address space is used for I/O registers and corresponding symbols are defined. Besides, despite that it is very rare to have GP the highest address, it would be nice because we enabled highest address printing on regular cases. gas/ChangeLog: * testsuite/gas/riscv/dis-addr-topaddr.s: New test for the top address (-1) printing. * testsuite/gas/riscv/dis-addr-topaddr-32.d: Likewise. * testsuite/gas/riscv/dis-addr-topaddr-64.d: Likewise. * testsuite/gas/riscv/dis-addr-topaddr-gp.s: New test for GP-relative addressing when GP is the highest address (-1). * testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Likewise. * testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (struct riscv_private_data): Add `to_print_addr' to enable printing the highest address. (maybe_print_address): Utilize `to_print_addr'. (riscv_disassemble_insn): Likewise.
2022-09-02RISC-V: PR29342, Fix RV32 disassembler address computationTsukasa OI1-1/+7
If either the base register is `zero', `tp' or `gp' and XLEN is 32, an incorrectly sign-extended address is produced when printing. This commit fixes this by fitting an address into a 32-bit value on RV32. Besides, H. Peter Anvin discovered that we have wrong address computation for JALR instruction (the initial bug is back in 2018). This commit also fixes that based on the idea of Palmer Dabbelt. gas/ pr29342 * testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix. * testsuite/gas/riscv/dis-addr-overflow.s: New testcase. * testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise. * testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise. opcodes/ pr29342 * riscv-dis.c (maybe_print_address): Fit address into 32-bit on RV32. (print_insn_args): Fix JALR address by adding EXTRACT_ITYPE_IMM.
2022-07-07RISC-V: Fix disassembling Zfinx with -M numericTsukasa OI1-1/+1
This commit fixes floating point operand register names from ABI ones to dynamically set ones. gas/ChangeLog: * testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of Zfinx extension and -M numeric disassembler option. * testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR names to disassemble Zfinx instructions.
2022-04-30opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblersThomas Hebb1-16/+12
Currently, the get_disassembler() implementations for riscv, csky, and rl78--and mep_print_insn() for mep--access ELF variants of union fields without first checking that the bfd actually represents an ELF. This causes undefined behavior and crashes when disassembling non-ELF files (the "binary" BFD, for example). Fix that.
2022-04-04opcodes/riscv: implement style support in the disassemblerAndrew Burgess1-72/+121
Update the RISC-V disassembler to supply style information. This allows objdump to apply syntax highlighting to the disassembler output (when the appropriate command line flag is used). Ignoring colours, there should be no other user visible changes in the output of the disassembler in either objdump or gdb. opcodes/ChangeLog: * disassembler.c (disassemble_init_for_target): Set created_styled_output for riscv. * riscv-dis.c: Changed throughout to use fprintf_styled_func instead of fprintf_func.
2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI1-0/+4
This commit adds 'Zicbop' hint instructions. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for new instruction class. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Add handling for new operand type 'f' (32-byte aligned pseudo S-type immediate for prefetch hints). (validate_riscv_insn): Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I, MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W, MASK_PREFETCH_W): New macros. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class INSN_CLASS_ZICBOP. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add handling for new operand type. * riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
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