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path: root/opcodes/riscv-dis.c
AgeCommit message (Expand)AuthorFilesLines
2018-08-30RISC-V: Allow instruction require more than one extensionJim Wilson1-1/+1
2018-07-30RISC-V: Set insn info fields correctly when disassembling.Jim Wilson1-0/+26
2018-03-03opcodes error messagesAlan Modra1-2/+2
2018-01-09RISC-V: Disassemble x0 based addresses as 0.Jim Wilson1-1/+1
2018-01-05RISC-V: Print symbol address for jalr w/ zero offset.Jim Wilson1-0/+2
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-07-25Fix typos in error and option messages in OPCODES library.Nick Clifton1-1/+1
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi1-1/+1
2017-05-04RISC-V: Fix disassemble for c.li, c.andi and c.addiwKito Cheng1-0/+1
2017-04-04RISC-V: Resurrect GP-relative disassembly hintsPalmer Dabbelt1-1/+1
2017-01-03Add fall through comment.Dilyan Palauzov1-0/+1
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman1-2/+6
2016-11-01Add support for RISC-V architecture.Nick Clifton1-0/+502