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2022-03-16Delete PowerPC macro insn supportAlan Modra1-18/+0
Let's hope this stays dead, but it's here as a patch separate from those that removed use of powerpc_macros just in case it needs to be resurrected. include/ * opcode/ppc.h (struct powerpc_macro): Delete declaration. (powerpc_macros, powerpc_num_macros): Likewise.. opcodes/ * ppc-opc.c (powerpc_macros, powerpc_num_macros): Delete. gas/ * config/tc-ppc.c (ppc_macro): Delete function. (ppc_macro_hash): Delete. (ppc_setup_opcodes, md_assemble): Delete macro support.
2022-03-16PowerPC SPE/SPE2 aliases in powerpc_macrosAlan Modra1-30/+27
* ppc-opc.c (powerpc_macros): Move "evsadd", "evssub", "evsabs", "evsnabs", "evsneg", "evsmul", "evsdiv", "evscmpgt", "evsgmplt", "evsgmpeq", "evscfui", "evscfsi", "evscfuf", "evscfsf", "evsctui", "evsctsi", "evsctuf", "evsctsf", "evsctuiz", "evsctsiz", "evststgt", "evststlt", "evststeq".. (powerpc_opcodes): ..to here. (powerpc_macros): Move "evdotphsssi", "evdotphsssia", "evdotpwsssi", and "evdotpwsssia".. (spe2_opcodes): ..to here.
2022-03-16PowerPC VLE extended instructions in powerpc_macrosAlan Modra1-13/+10
This moves VLE insn out of the macro table. "e_slwi" and "e_srwi" already exist in vle_opcodes as distinct instructions rather than encodings of e_rlwinm. opcodes/ * ppc-opc.c (vle_opcodes): Typo fix e_rlwinm operand. Add "e_inslwi", "e_insrwi", "e_rotlwi", "e_rotrwi", "e_clrlwi", "e_clrrwi", "e_extlwi", "e_extrwi", and "e_clrlslwi". (powerpc_macros): Delete same. Delete "e_slwi" and "e_srwi" too. gas/ * testsuite/gas/ppc/vle-simple-5.d: Update.
2022-03-16PowerPC32 extended instructions in powerpc_macrosAlan Modra1-25/+296
As for PowerPC64, move instructions to the main opcode table. opcodes/ * ppc-opc.c (insert_crwn, extract_crwn, insert_elwn, extract_elwn), (insert_erwn, extract_erwn, insert_erwb, extract_erwb), (insert_cslwn, extract_cslwb, insert_ilwb, extract_ilwn), (insert_irwb, extract_irwn, insert_rrwn, extract_rrwn), (insert_slwn, extract_slwn, insert_srwn, extract_srwn): New functions. (CRWn, ELWn, ERWn, ERWb, CSLWb, CSLWn, ILWn, ILWb, IRWn, IRWb), (RRWn, SLWn, SRWn): Define and add powerpc_operands entries. (MMB_MASK, MME_MASK, MSHMB_MASK): Define. (powerpc_opcodes): Add "inslwi", "insrwi", "rotrwi", "clrrwi", "slwi", "srwi", "extlwi", "extrwi", "sli", "sri" and corresponding record (ie. dot suffix) forms. (powerpc_macros): Delete same. gas/ * testsuite/gas/ppc/476.d: Update. * testsuite/gas/ppc/simpshft.d: Update.
2022-03-16PowerPC64 extended instructions in powerpc_macrosAlan Modra1-19/+245
The extended instructions implemented in powerpc_macros aren't used by the disassembler. That means instructions like "sldi r3,r3,2" appear in disassembly as "rldicr r3,r3,2,61", which is annoying since many other extended instructions are shown. Note that some of the instructions moved out of the macro table to the opcode table won't appear in disassembly, because they are aliases rather than a subset of the underlying raw instruction. If enabled, rotrdi, extrdi, extldi, clrlsldi, and insrdi would replace all occurrences of rotldi, rldicl, rldicr, rldic and rldimi. (Or many occurrences in the case of clrlsldi if n <= b was added to the extract functions.) The patch also fixes a small bug in opcode sanity checking. include/ * opcode/ppc.h (PPC_OPSHIFT_SH6): Define. opcodes/ * ppc-opc.c (insert_erdn, extract_erdn, insert_eldn, extract_eldn), (insert_crdn, extract_crdn, insert_rrdn, extract_rrdn), (insert_sldn, extract_sldn, insert_srdn, extract_srdn), (insert_erdb, extract_erdb, insert_csldn, extract_csldb), (insert_irdb, extract_irdn): New functions. (ELDn, ERDn, ERDn, RRDn, SRDn, ERDb, CSLDn, CSLDb, IRDn, IRDb): Define and add associated powerpc_operands entries. (powerpc_opcodes): Add "rotrdi", "srdi", "extrdi", "clrrdi", "sldi", "extldi", "clrlsldi", "insrdi" and corresponding record (ie. dot suffix) forms. (powerpc_macros): Delete same from here. gas/ * config/tc-ppc.c (insn_validate): Don't modify value passed to operand->insert for PPC_OPERAND_PLUS1 when calculating mask. Handle PPC_OPSHIFT_SH6. * testsuite/gas/ppc/prefix-reloc.d: Update. * testsuite/gas/ppc/simpshft.d: Update. ld/ * testsuite/ld-powerpc/elfv2so.d: Update. * testsuite/ld-powerpc/notoc.d: Update. * testsuite/ld-powerpc/notoc3.d: Update. * testsuite/ld-powerpc/tlsdesc2.d: Update. * testsuite/ld-powerpc/tlsget.d: Update. * testsuite/ld-powerpc/tlsget2.d: Update. * testsuite/ld-powerpc/tlsopt5.d: Update. * testsuite/ld-powerpc/tlsopt6.d: Update.
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2021-09-25PowerPC: Enable mfppr mfppr32, mtppr and mtppr32 extended mnemonics on POWER5Peter Bergner1-4/+4
SPR 896 and the mfppr mfppr32, mtppr and mtppr32 extended mnemonics were added in ISA 2.03, so enable them on POWER5 and later. opcodes/ * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable on POWER5 and later. gas/ * testsuite/gas/ppc/power5.s: New test. * testsuite/gas/ppc/power5.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. * testsuite/gas/ppc/power7.s: Remove tests for mfppr, mfppr32, mtppr and mtppr32. * testsuite/gas/ppc/power7.d: Likewise.
2021-06-17powerpc: move cell "or rx,rx,rx" hintsAlan Modra1-5/+5
* ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location in table.
2021-05-29PowerPC table driven -Mraw disassemblyAlan Modra1-1605/+1601
opcodes/ * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many. Don't special case PPC_OPCODE_RAW. (lookup_prefix): Likewise. (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and.. (print_insn_powerpc): ..update caller. * ppc-opc.c (EXT): Define. (powerpc_opcodes): Mark extended mnemonics with EXT. (prefix_opcodes, vle_opcodes): Likewise. (XISEL, XISEL_MASK): Add cr field and simplify. (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort all isel variants to where the base mnemonic belongs. Sort dstt, dststt and dssall. gas/ * testsuite/gas/ppc/raw.s, * testsuite/gas/ppc/raw.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2021-05-27PowerPC: Add new xxmr and xxlnot extended mnemonicsPeter Bergner1-0/+2
opcodes/ * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics. gas/ * testsuite/gas/ppc/vsx.d <xxmr, xxlnot>: Add tests. * testsuite/gas/ppc/vsx.s: Likewise.
2021-04-08PR27684, PowerPC missing mfsprg0 and othersAlan Modra1-4/+5
PR 27684 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
2021-04-08PR27676, PowerPC missing extended dcbt, dcbtst mnemonicsAlan Modra1-7/+82
Note that this doesn't implement the ISA to the letter regarding dcbtds (and dcbtstds), which says that the TH field may be zero. That doesn't make sense because allowing TH=0 would mean you no long have a dcbtds but rather a dcbtct instruction. I'm interpreting the ISA wording about allowing TH=0 to mean that the TH field of dcbtds is optional (in which case the TH value is 0b1000). opcodes/ PR 27676 * ppc-opc.c (DCBT_EO): Move earlier. (insert_thct, extract_thct, insert_thds, extract_thds): New functions. (powerpc_operands): Add THCT and THDS entries. (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds. gas/ * testsuite/gas/ppc/pr27676.d, * testsuite/gas/ppc/pr27676.s: New test. * testsuite/gas/ppc/ppc.exp: Run it. * testsuite/gas/ppc/dcbt.d: Update. * testsuite/gas/ppc/power4_32.d: Update.
2021-04-01PR27675, PowerPC missing extended mnemonic mfummcr2Alan Modra1-0/+2
PR 27675 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
2021-03-25PR27647 PowerPC extended conditional branch mnemonicsAlan Modra1-476/+477
opcodes/ PR 27647 * ppc-opc.c (XLOCB_MASK): Delete. (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using XLBH_MASK. (powerpc_opcodes): Accept a BH field on all extended forms of bclr, bclrl, bcctr, bcctrl, bctar, bctarl. gas/ PR 27647 * testsuite/gas/ppc/a2.d: Update expected output. * testsuite/gas/ppc/power8.d: Likewise.
2021-01-09POWER10: Add Return-Oriented Programming instructionsPeter Bergner1-1/+45
POWER10 adds some return-oriented programming (ROP) instructions and this patch adds support for them. You will notice that they are enabled for POWER8 and later, not just POWER10 and later. This is on purpose. This allows the instructions to be added to POWER8 binaries that can be run on POWER8, POWER9 and POWER10 cpus. On POWER8 and POWER9, these instructions just act as nop's. opcodes/ * ppc-opc.c (insert_dw, (extract_dw): New functions. (DW, (XRC_MASK): Define. (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics. gas/ * testsuite/gas/ppc/rop-checks.d, * testsuite/gas/ppc/rop-checks.l, * testsuite/gas/ppc/rop-checks.s, * testsuite/gas/ppc/rop.d, * testsuite/gas/ppc/rop.s: New tests. * testsuite/gas/ppc/ppc.exp: Run them.
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-08-19Correct vcmpsq, vcmpuq and xvtlsbb BF fieldAlan Modra1-3/+3
These shouldn't be optional. The record form of vector instructions set CR6, giving an expectation that omitting BF should be the same as specifying CR6. opcodes/ * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq, vcmpuq and xvtlsbb. gas/ * testsuite/gas/ppc/int128.s: Correct vcmpuq. * testsuite/gas/ppc/int128.d: Update. * testsuite/gas/ppc/xvtlsbb.d: Update.
2020-08-18PowerPC: Rename xvcvbf16sp to xvcvbf16spnPeter Bergner1-1/+1
The xvcvbf16sp mnemonic has been renamed to xvcvbf16spn, to be consistent with the other non-signaling conversion instructions which all end with "n". opcodes/ * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this... <xvcvbf16spn>: ...to this. gas/ * testsuite/gas/ppc/vsx4.s: Update test to use new mnemonic. * testsuite/gas/ppc/vsx4.d: Likewise.
2020-08-11PowerPC CELL cctp*Alan Modra1-4/+7
* ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
2020-08-10Implement missing powerpc mtspr and mfspr extended insnsAlan Modra1-6/+156
* ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended instructions.
2020-08-10Implement missing powerpc extended mnemonicsAlan Modra1-7/+11
gas/ * testsuite/gas/ppc/power8.d, * testsuite/gas/ppc/power8.s: Add miso. * testsuite/gas/ppc/power9.d, * testsuite/gas/ppc/power8.s: Add exser, msgsndu, msgclru. opcodes/ * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru. Enable icbt for power5, miso for power8.
2020-08-10Prioritise mtfprd and mtvrd over mtvsrd in PowerPC disassemblyAlan Modra1-2/+2
gas/ * testsuite/gas/ppc/power8.d: Update. * testsuite/gas/ppc/vsx2.d: Update. opcodes/ * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over mtvsrd, and similarly for mfvsrd.
2020-05-19Power10 dcbf, sync, and wait extensions.Peter Bergner1-26/+226
opcodes/ * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new WC values on POWER10 sync, dcbf and wait instructions. (insert_pl, extract_pl): New functions. (L2OPT, LS, WC): Use insert_ls and extract_ls. (LS3): New , 3-bit L for sync. (LS3, L3OPT): New, 3-bit L for sync and dcbf. (SC2, PL): New, 2-bit SC and PL for sync and wait. (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks. (XOPL3, XWCPL, XSYNCLS): New opcode macros. (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync, plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics. <wait>: Enable PL operand on POWER10. <dcbf>: Enable L3OPT operand on POWER10. <sync>: Enable SC2 operand on POWER10. gas/ * testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests. * testsuite/gas/ppc/power9.d: Likewise. * testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync, pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync, sync, wait, waitrsv>: Add tests. * testsuite/gas/ppc/power10.d: Likewise.
2020-05-11Power10 VSX scalar min-max-compare quad precision operationsAlan Modra1-0/+11
opcodes/ * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp, xsmaxcqp, xsmincqp. gas/ * testsuite/gas/ppc/scalarquad.d, * testsuite/gas/ppc/scalarquad.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 VSX load/store rightmost element operationsAlan Modra1-0/+16
opcodes/ * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx, stxvrbx, stxvrhx, stxvrwx, stxvrdx. gas/ * testsuite/gas/ppc/rightmost.d, * testsuite/gas/ppc/rightmost.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 test lsb by byte operationAlan Modra1-0/+1
opcodes/ * ppc-opc.c (powerpc_opcodes): Add xvtlsbb. gas/ * testsuite/gas/ppc/xvtlsbb.d, * testsuite/gas/ppc/xvtlsbb.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 string operationsAlan Modra1-0/+10
opcodes/ * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr, vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr.. gas/ * testsuite/gas/ppc/stringop.d, * testsuite/gas/ppc/stringop.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 Set boolean extensionPeter Bergner1-0/+8
opcodes/ * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New mnemonics. gas/ * testsuite/gas/ppc/set_bool.d, * testsuite/gas/ppc/set_bool.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 bit manipulation operationsAlan Modra1-1/+20
opcodes/ * ppc-opc.c (UIM8, P_U8XX4_MASK): Define. (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm, vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm. (prefix_opcodes): Add xxeval. gas/ * testsuite/gas/ppc/bitmanip.d, * testsuite/gas/ppc/bitmanip.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 VSX PCV generate operationsAlan Modra1-0/+4
opcodes/ * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm, xxgenpcvwm, xxgenpcvdm. gas/ * testsuite/gas/ppc/genpcv.d, * testsuite/gas/ppc/genpcv.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 VSX Mask Manipulation OperationsAlan Modra1-1/+27
opcodes/ * ppc-opc.c (MP, VXVAM_MASK): Define. (VXVAPS_MASK): Use VXVA_MASK. (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm, vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm, vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm, vcntmbb, vcntmbh, vcntmbw, vcntmbd. gas/ * testsuite/gas/ppc/maskmanip.d, * testsuite/gas/ppc/maskmanip.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 Reduced precision outer product operationsAlan Modra1-4/+204
include/ * opcode/ppc.h (PPC_OPERAND_ACC): Define. Renumber following PPC_OPERAND defines. opcodes/ * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): New functions. (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK, YMSK2, XA6a, XA6ap, XB6a entries. (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define. (PPCVSX4): Define. (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16. (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp, pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8, pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2, pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp, pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp, pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn, pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn. gas/ * config/tc-ppc.c (pre_defined_registers): Add accumulators. (md_assemble): Check acc specified in correct operand. * testsuite/gas/ppc/outerprod.d, * testsuite/gas/ppc/outerprod.s, * testsuite/gas/ppc/vsx4.d, * testsuite/gas/ppc/vsx4.s: New tests. * testsuite/gas/ppc/ppc.exp: Run them.
2020-05-11Power10 SIMD permute class operationsAlan Modra1-3/+114
opcodes/ * ppc-opc.c (insert_imm32, extract_imm32): New functions. (insert_xts, extract_xts): New functions. (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define. (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define. (VXRC_MASK, VXSH_MASK): Define. (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx, vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx, vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx, vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx, vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq. (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb, xxblendvh, xxblendvw, xxblendvd, xxpermx. gas/ * testsuite/gas/ppc/simd_perm.d, * testsuite/gas/ppc/simd_perm.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 128-bit binary integer operationsAlan Modra1-0/+36
opcodes/ * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi, vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd, vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd, vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz, xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq. gas/ * testsuite/gas/ppc/int128.d, * testsuite/gas/ppc/int128.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 VSX 32-byte storage accessAlan Modra1-1/+37
bfd/ * elf64-ppc.c (xlate_pcrel_opt): Handle lxvp and stxvp. opcodes/ * ppc-opc.c (insert_xtp, extract_xtp): New functions. (XTP, DQXP, DQXP_MASK): Define. (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx. (prefix_opcodes): Add plxvp and pstxvp. gas/ * testsuite/gas/ppc/vsx_32byte.d, * testsuite/gas/ppc/vsx_32byte.s: New test. * testsuite/gas/ppc/ppc.exp: Run it. ld/ * testsuite/ld-powerpc/pcrelopt.s: Add lxvp and stxvp. * testsuite/ld-powerpc/pcrelopt.d: Update.
2020-05-11Power10 vector integer multiply, divide, modulo insnsAlan Modra1-0/+17
opcodes/ * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld, vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw, vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd. gas/ * testsuite/gas/ppc/vec_mul.s, * testsuite/gas/ppc/vec_mul.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 byte reverse instructionsPeter Bergner1-0/+6
opcodes/ * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics. gas/ * testsuite/gas/ppc/byte_rev.d, * testsuite/gas/ppc/byte_rev.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11Power10 Copy/Paste ExtensionsPeter Bergner1-2/+31
opcodes/ * opcodes/ppc-opc.c (insert_l1opt, extract_l1opt): New functions. (L1OPT): Define. (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10. gas/ * testsuite/gas/ppc/power10.d: Add paste. tests. * testsuite/gas/ppc/power10.s: Likewise.
2020-05-11Power10 Add new L operand to the slbiag instructionPeter Bergner1-1/+3
opcodes/ * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand. gas/ * testsuite/gas/ppc/power10.s: New test. * testsuite/gas/ppc/power10.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11PowerPC Rename powerxx to power10Alan Modra1-28/+28
Now that ISA3.1 is out we can finish with the powerxx silliness. bfd/ * elf64-ppc.c: Rename powerxx to power10 throughout. gas/ * config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10 renaming. * testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in place of -mfuture/-Mfuture. * testsuite/gas/ppc/prefix-pcrel.d: Likewise. * testsuite/gas/ppc/prefix-reloc.d: Likewise. gold/ * powerpc.cc: Rename powerxx to power10 throughout. include/ * elf/ppc64.h: Update comment. * opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX. ld/ * testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in place of -mfuture/-Mfuture. * testsuite/ld-powerpc/notoc2.d: Likewise. * testsuite/ld-powerpc/powerpc.exp: Likewise. * testsuite/ld-powerpc/tlsgd.d: Likewise. * testsuite/ld-powerpc/tlsie.d: Likewise. * testsuite/ld-powerpc/tlsld.d: Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power10" entry. (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming. * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-23ppc: misc minor build correctionsJan Beulich1-3/+3
Avoid shadowing a libiberty symbol (which oldish gcc warns about by default), and allow building cleanly on 32-bit distros.
2019-12-18More signed overflow fixesAlan Modra1-2/+2
The arc fix in create_map avoiding signed overflow by casting an unsigned char to unsigned int before shifting, shows one of the dangers of blinding doing that. The problem in this case was that the variable storing the value, newAuxRegister->address, was a long. Using the unsigned cast meant that the 32-bit value was zero extended when long is 64 bits. Previously we had a sign extension. Net result was that comparisons in arcExtMap_auxRegName didn't match. Of course, I could have cast the 32-bit unsigned value back to signed before storing in a long, but it's neater to just use an unsigned int for the address. opcodes/ * alpha-opc.c (OP): Avoid signed overflow. * arm-dis.c (print_insn): Likewise. * mcore-dis.c (print_insn_mcore): Likewise. * pj-dis.c (get_int): Likewise. * ppc-opc.c (EBD15, EBD15BI): Likewise. * score7-dis.c (s7_print_insn): Likewise. * tic30-dis.c (print_insn_tic30): Likewise. * v850-opc.c (insert_SELID): Likewise. * vax-dis.c (print_insn_vax): Likewise. * arc-ext.c (create_map): Likewise. (struct ExtAuxRegister): Make "address" field unsigned int. (arcExtMap_auxRegName): Pass unsigned address. (dump_ARC_extmap): Adjust. * arc-ext.h (arcExtMap_auxRegName): Update prototype.
2019-06-12Remove the ldmx mnemonic that never made it into POWER9.Peter Bergner1-2/+0
opcodes/ * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic. gas/ * testsuite/gas/ppc/power9.d: Delete ldmx tests. * testsuite/gas/ppc/power9.s: Likewise.
2019-05-24PowerPC D-form prefixed loads and storesPeter Bergner1-4/+184
opcodes/ * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34), (insert_pcrel, extract_pcrel, extract_pcrel0): New functions. (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment. (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0, XTOP>): Define and add entries. (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define. (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw, pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd, plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq. gas/ * config/tc-ppc.c (ppc_insert_operand): Only sign extend fields that are 32-bits or smaller. * messages.c (as_internal_value_out_of_range): Do not truncate variables and use BFD_VMA_FMT to print them. * testsuite/gas/ppc/prefix-pcrel.s, * testsuite/gas/ppc/prefix-pcrel.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2019-05-24PowerPC add initial -mfuture instruction supportPeter Bergner1-0/+24
This patch adds initial 64-bit insn assembler/disassembler support. The only instruction added is "pnop" along with the automatic aligning of prefix instruction so they do not cross 64-byte boundaries. include/ * dis-asm.h (WIDE_OUTPUT): Define. * opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare. (PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX), (PPC_PREFIX_P, PPC_PREFIX_SEG): Define. opcodes/ * ppc-dis.c (ppc_opts): Add "future" entry. (PREFIX_OPCD_SEGS): Define. (prefix_opcd_indices): New array. (disassemble_init_powerpc): Initialize prefix_opcd_indices. (lookup_prefix): New function. (print_insn_powerpc): Handle 64-bit prefix instructions. * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK), (PMRR, POWERXX): Define. (prefix_opcodes): New instruction table. (prefix_num_opcodes): New constant. binutils/ * objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes. (struct insn_label_list): New. (insn_labels, free_insn_labels): New variables. (ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs. (ppc_frob_label, ppc_new_dot_label): Move functions earlier in file and call ppc_record_label. (md_assemble): Handle 64-bit prefix instructions. Align labels that are on the same line as a prefix instruction. * config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to later in the file. (md_start_line_hook): Define. (ppc_start_line_hook): Declare. * testsuite/gas/ppc/prefix-align.d, * testsuite/gas/ppc/prefix-align.s: New test. * testsuite/gas/ppc/ppc.exp: Run new test.
2019-04-05PowerPC bc extended branch mnemonics and "y" hintsAlan Modra1-141/+141
This patch fixes a problem with disassembly of branch instructions for processors complying with PowerPC ISA versions prior to version 2.0, ie. those that use "y" bit branch taken hints. Many of the extended bcctr and bclr mnemonics that should have disassembled with a "-" suffix, ie. not taken, did not display the "-" due to the ordering in powerpc_opcodes. I believe it's been that way from the original 85dcf36d72b commit of ppc-opc.c. I've also added a BH field (optional) to a few opcodes. This gives better disassembly in raw mode, showing the branch taken hint in the mnemonic as is done for bc. It would be reasonable to add a BH field to all bcctr, bclr, and bctar extended mnemonics but that runs into a small difficulty: Currently we print all or none of the optional operands. That means for example that "bgectr cr2" would display as "bgectr cr2,0" if a BH field is added to bgectr. * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK. (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics to favour printing of "-" branch hint when using the "y" bit. Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2019-04-04Add extended mnemonics for bctar. Fix setting of 'at' branch hints.Peter Bergner1-49/+262
opcodes/ PR gas/24349 * ppc-opc.c (valid_bo_pre_v2): Add comments. (valid_bo_post_v2): Add support for 'at' branch hints. (insert_bo): Only error on branch on ctr. (get_bo_hint_mask): New function. (insert_boe): Add new 'branch_taken' formal argument. Add support for inserting 'at' branch hints. (extract_boe): Add new 'branch_taken' formal argument. Add support for extracting 'at' branch hints. (insert_bom, extract_bom, insert_bop, extract_bop): New functions. (BOE): Delete operand. (BOM, BOP): New operands. (RM): Update value. (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-, bcctrl-, bctar-, bctarl->: Replace BOE with BOM. (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+, bcctrl+, bctar+, bctarl+>: Replace BOE with BOP. <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, bttarl+>: New extended mnemonics. gas/ PR gas/24349 * testsuite/gas/ppc/power8.s: (bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, bttarl+): Add tests of extended mnemonics. * testsuite/gas/ppc/power8.d: Likewise. Update previous bctar tests to expect new extended mnemonics. * testsuite/gas/ppc/a2.s: <bc, bc-, bc+, bcl, bcl-, bcl+>: Update test to not use illegal BO value. Use a more convenient BI value. * testsuite/gas/ppc/a2.d: Update tests for new expect output.
2019-03-28PR24390, Don't decode mtfsb field as a cr fieldAlan Modra1-5/+9
"mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit. So for backwards compatibility accept cr field expressions when assembling mtfsb operands, but disassemble to a plain number. PR 24390 include/ * opcode/ppc.h (PPC_OPERAND_CR_REG): Comment. opcodes/ * ppc-opc.c (BTF): Define. (powerpc_opcodes): Use for mtfsb*. * ppc-dis.c (print_insn_powerpc): Print fields with both PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. gas/ * testsuite/gas/ppc/476.d: Update mtfsb*. * testsuite/gas/ppc/a2.d: Likewise.
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
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