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| author | Alan Modra <amodra@gmail.com> | 2019-03-28 10:36:55 +1030 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2019-03-28 15:21:05 +1030 |
| commit | 96a86c01d119372f4af5aff2501d3104e6c1a8e3 (patch) | |
| tree | cbd1ac115b85d52e073ee0ca7b2ffd31901a3395 /opcodes/ppc-opc.c | |
| parent | 072029171354eee0e2f90527196ddda5a85e98c1 (diff) | |
| download | gdb-96a86c01d119372f4af5aff2501d3104e6c1a8e3.zip gdb-96a86c01d119372f4af5aff2501d3104e6c1a8e3.tar.gz gdb-96a86c01d119372f4af5aff2501d3104e6c1a8e3.tar.bz2 | |
PR24390, Don't decode mtfsb field as a cr field
"mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately
glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit.
So for backwards compatibility accept cr field expressions when
assembling mtfsb operands, but disassemble to a plain number.
PR 24390
include/
* opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
opcodes/
* ppc-opc.c (BTF): Define.
(powerpc_opcodes): Use for mtfsb*.
* ppc-dis.c (print_insn_powerpc): Print fields with both
PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
gas/
* testsuite/gas/ppc/476.d: Update mtfsb*.
* testsuite/gas/ppc/a2.d: Likewise.
Diffstat (limited to 'opcodes/ppc-opc.c')
| -rw-r--r-- | opcodes/ppc-opc.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 3032631..c4b6c16 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -1837,8 +1837,12 @@ const struct powerpc_operand powerpc_operands[] = #define BT BH + 1 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT }, + /* The BT field in a mtfsb0 or mtfsb1 instruction. */ +#define BTF BT + 1 + { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG }, + /* The BI16 field in a BD8 form instruction. */ -#define BI16 BT + 1 +#define BI16 BTF + 1 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT }, /* The BI32 field in a BD15 form instruction. */ @@ -7381,8 +7385,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, -{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}}, -{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}}, +{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BTF}}, +{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BTF}}, {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, {"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, @@ -7395,8 +7399,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, {"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, -{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}}, -{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}}, +{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BTF}}, +{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BTF}}, {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |