| Age | Commit message (Collapse) | Author | Files | Lines |
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* config/tc-mips.c (mips_set_options): Add ase_mcu.
(mips_opts): Initialise ase_mcu to -1.
(ISA_SUPPORTS_MCU_ASE): New macro.
(MIPS_CPU_ASE_MCU): Likewise.
(is_opcode_valid): Handle MCU.
(macro_build, macro): Likewise.
(validate_mips_insn, validate_micromips_insn): Likewise.
(mips_ip): Likewise.
(options): Add OPTION_MCU and OPTION_NO_MCU.
(md_longopts): Add mmcu and mno-mcu.
(md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU.
(mips_after_parse_args): Handle MCU.
(s_mipsset): Likewise.
(md_show_usage): Handle MCU options.
* doc/as.texinfo: Document -mmcu and -mno-mcu options.
* doc/c-mips.texi: Likewise, and document ".set mcu" and
".set nomcu" directives.
gas/testsuite/
* gas/mips/micromips@mcu.d: New test.
* gas/mips/mcu.d: Likewise.
* gas/mips/mcu.s: New test source.
* gas/mips/mips.exp: Run the new tests.
include/opcode/
* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
(INSN_ASE_MASK): Add the MCU bit.
(INSN_MCU): New macro.
(M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
opcodes/
* mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
and "mips64r2".
(print_insn_args, print_insn_micromips): Handle MCU.
* micromips-opc.c (MC): New macro.
(micromips_opcodes): Add "aclr", "aset" and "iret".
* mips-opc.c (MC): New macro.
(mips_builtin_opcodes): Add "aclr", "aset" and "iret".
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2011-02-25 Chao-ying Fu <fu@mips.com>
Ilie Garbacea <ilie@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* archures.c (bfd_mach_mips_micromips): New macro.
* cpu-mips.c (I_micromips): New enum value.
(arch_info_struct): Add bfd_mach_mips_micromips.
* elfxx-mips.h (_bfd_mips_elf_is_target_special_symbol): New
prototype.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(gprel16_reloc_p): Handle microMIPS ASE.
(literal_reloc_p): New function.
* elf32-mips.c (elf_micromips_howto_table_rel): New variable.
(_bfd_mips_elf32_gprel16_reloc): Handle microMIPS ASE.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(mips_elf_gprel32_reloc): Update comment.
(micromips_reloc_map): New variable.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(mips_elf32_rtype_to_howto): Likewise.
(mips_info_to_howto_rel): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
(bfd_elf32_bfd_relax_section): Likewise.
* elf64-mips.c (micromips_elf64_howto_table_rel): New variable.
(micromips_elf64_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf64_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf64_bfd_reloc_name_lookup): Likewise.
(mips_elf64_rtype_to_howto): Likewise.
(bfd_elf64_bfd_is_target_special_symbol): Define.
* elfn32-mips.c (elf_micromips_howto_table_rel): New variable.
(elf_micromips_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf32_bfd_reloc_name_lookup): Likewise.
(mips_elf_n32_rtype_to_howto): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
* elfxx-mips.c (LA25_LUI_MICROMIPS_1): New macro.
(LA25_LUI_MICROMIPS_2): Likewise.
(LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise.
(LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise.
(TLS_RELOC_P): Handle microMIPS ASE.
(mips_elf_create_stub_symbol): Adjust value of stub symbol if
target is a microMIPS function.
(micromips_reloc_p): New function.
(micromips_reloc_shuffle_p): Likewise.
(got16_reloc_p, call16_reloc_p): Handle microMIPS ASE.
(got_disp_reloc_p, got_page_reloc_p): New functions.
(got_ofst_reloc_p): Likewise.
(got_hi16_reloc_p, got_lo16_reloc_p): Likewise.
(call_hi16_reloc_p, call_lo16_reloc_p): Likewise.
(hi16_reloc_p, lo16_reloc_p, jal_reloc_p): Handle microMIPS ASE.
(micromips_branch_reloc_p): New function.
(tls_gd_reloc_p, tls_ldm_reloc_p): Likewise.
(tls_gottprel_reloc_p): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(_bfd_mips_elf_lo16_reloc): Handle microMIPS ASE.
(mips_tls_got_index, mips_elf_got_page): Likewise.
(mips_elf_create_local_got_entry): Likewise.
(mips_elf_relocation_needs_la25_stub): Likewise.
(mips_elf_calculate_relocation): Likewise.
(mips_elf_perform_relocation): Likewise.
(_bfd_mips_elf_symbol_processing): Likewise.
(_bfd_mips_elf_add_symbol_hook): Likewise.
(_bfd_mips_elf_link_output_symbol_hook): Likewise.
(mips_elf_add_lo16_rel_addend): Likewise.
(_bfd_mips_elf_check_relocs): Likewise.
(mips_elf_adjust_addend): Likewise.
(_bfd_mips_elf_relocate_section): Likewise.
(mips_elf_create_la25_stub): Likewise.
(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
(_bfd_mips_elf_gc_sweep_hook): Likewise.
(_bfd_mips_elf_is_target_special_symbol): New function.
(mips_elf_relax_delete_bytes): Likewise.
(opcode_descriptor): New structure.
(RA): New macro.
(OP32_SREG, OP32_TREG, OP16_VALID_REG): Likewise.
(b_insns_32, bc_insn_32, bz_insn_32, bzal_insn_32): New variables.
(beq_insn_32): Likewise.
(b_insn_16, bz_insn_16): New variables.
(BZC32_REG_FIELD): New macro.
(bz_rs_insns_32, bz_rt_insns_32): New variables.
(bzc_insns_32, bz_insns_16):Likewise.
(BZ16_REG, BZ16_REG_FIELD): New macros.
(jal_insn_32_bd16, jal_insn_32_bd32): New variables.
(jal_x_insn_32_bd32): Likewise.
(j_insn_32, jalr_insn_32): Likewise.
(ds_insns_32_bd16, ds_insns_32_bd32): Likewise.
(jalr_insn_16_bd16, jalr_insn_16_bd32, jr_insn_16): Likewise.
(JR16_REG): New macro.
(ds_insns_16_bd16): New variable.
(lui_insn): Likewise.
(addiu_insn, addiupc_insn): Likewise.
(ADDIUPC_REG_FIELD): New macro.
(MOVE32_RD, MOVE32_RS): Likewise.
(MOVE16_RD_FIELD, MOVE16_RS_FIELD): Likewise.
(move_insns_32, move_insns_16): New variables.
(nop_insn_32, nop_insn_16): Likewise.
(MATCH): New macro.
(find_match): New function.
(check_br16_dslot, check_br32_dslot): Likewise.
(check_br16, check_br32): Likewise.
(IS_BITSIZE): New macro.
(check_4byte_branch): New function.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips_elf_merge_private_bfd_data): Disallow linking MIPS16
and microMIPS modules together.
(_bfd_mips_elf_print_private_bfd_data): Handle microMIPS ASE.
* reloc.c (BFD_RELOC_MICROMIPS_7_PCREL_S1): New relocation.
(BFD_RELOC_MICROMIPS_10_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_16_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_GPREL16): Likewise.
(BFD_RELOC_MICROMIPS_JMP, BFD_RELOC_MICROMIPS_HI16): Likewise.
(BFD_RELOC_MICROMIPS_HI16_S): Likewise.
(BFD_RELOC_MICROMIPS_LO16): Likewise.
(BFD_RELOC_MICROMIPS_LITERAL): Likewise.
(BFD_RELOC_MICROMIPS_GOT16): Likewise.
(BFD_RELOC_MICROMIPS_CALL16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_HI16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_LO16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_SUB): Likewise.
(BFD_RELOC_MICROMIPS_GOT_PAGE): Likewise.
(BFD_RELOC_MICROMIPS_GOT_OFST): Likewise.
(BFD_RELOC_MICROMIPS_GOT_DISP): Likewise.
(BFD_RELOC_MICROMIPS_HIGHEST): Likewise.
(BFD_RELOC_MICROMIPS_HIGHER): Likewise.
(BFD_RELOC_MICROMIPS_SCN_DISP): Likewise.
(BFD_RELOC_MICROMIPS_JALR): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GD): Likewise.
(BFD_RELOC_MICROMIPS_TLS_LDM): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GOTTPREL): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_LO16): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
binutils/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* readelf.c (get_machine_flags): Handle microMIPS ASE.
(get_mips_symbol_other): Likewise.
gas/
2011-02-25 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.h (mips_segment_info): Add one bit for
microMIPS.
(TC_LABEL_IS_LOCAL): New macro.
(mips_label_is_local): New prototype.
* config/tc-mips.c (S0, S7): New macros.
(emit_branch_likely_macro): New variable.
(mips_set_options): Add micromips.
(mips_opts): Initialise micromips to -1.
(file_ase_micromips): New variable.
(CPU_HAS_MICROMIPS): New macro.
(hilo_interlocks): Set for microMIPS too.
(gpr_interlocks): Likewise.
(cop_interlocks): Likewise.
(cop_mem_interlocks): Likewise.
(HAVE_CODE_COMPRESSION): New macro.
(micromips_op_hash): New variable.
(micromips_nop16_insn, micromips_nop32_insn): New variables.
(NOP_INSN): Handle microMIPS ASE.
(mips32_to_micromips_reg_b_map): New macro.
(mips32_to_micromips_reg_c_map): Likewise.
(mips32_to_micromips_reg_d_map): Likewise.
(mips32_to_micromips_reg_e_map): Likewise.
(mips32_to_micromips_reg_f_map): Likewise.
(mips32_to_micromips_reg_g_map): Likewise.
(mips32_to_micromips_reg_l_map): Likewise.
(mips32_to_micromips_reg_n_map): Likewise.
(mips32_to_micromips_reg_h_map): New variable.
(mips32_to_micromips_reg_m_map): Likewise.
(mips32_to_micromips_reg_q_map): Likewise.
(micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_to_32_reg_b_map): New macro.
(micromips_to_32_reg_c_map): Likewise.
(micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map): Likewise.
(micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map): Likewise.
(micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_n_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): New macros.
(RELAX_DELAY_SLOT_16BIT): New macro.
(RELAX_DELAY_SLOT_SIZE_FIRST): Likewise.
(RELAX_DELAY_SLOT_SIZE_SECOND): Likewise.
(RELAX_MICROMIPS_ENCODE, RELAX_MICROMIPS_P): New macros.
(RELAX_MICROMIPS_TYPE, RELAX_MICROMIPS_AT): Likewise.
(RELAX_MICROMIPS_U16BIT, RELAX_MICROMIPS_UNCOND): Likewise.
(RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise.
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16): Likewise.
(RELAX_MICROMIPS_MARK_TOOFAR16): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise.
(RELAX_MICROMIPS_TOOFAR32): Likewise.
(RELAX_MICROMIPS_MARK_TOOFAR32): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise.
(INSERT_OPERAND, EXTRACT_OPERAND): Handle microMIPS ASE.
(mips_macro_warning): Add delay_slot_16bit_p, delay_slot_32bit_p,
fsize and insns.
(mips_mark_labels): New function.
(mips16_small, mips16_ext): Remove variables, replacing with...
(forced_insn_size): ... this.
(append_insn, mips16_ip): Update accordingly.
(micromips_insn_length): New function.
(insn_length): Return the length of microMIPS instructions.
(mips_record_mips16_mode): Rename to...
(mips_record_compressed_mode): ... this. Handle microMIPS ASE.
(install_insn): Handle microMIPS ASE.
(reglist_lookup): New function.
(is_size_valid, is_delay_slot_valid): Likewise.
(md_begin): Handle microMIPS ASE.
(md_assemble): Likewise. Update for append_insn interface change.
(micromips_reloc_p): New function.
(got16_reloc_p): Handle microMIPS ASE.
(hi16_reloc_p): Likewise.
(lo16_reloc_p): Likewise.
(jmp_reloc_p): New function.
(jalr_reloc_p): Likewise.
(matching_lo_reloc): Handle microMIPS ASE.
(insn_uses_reg, reg_needs_delay): Likewise.
(mips_move_labels): Likewise.
(mips16_mark_labels): Rename to...
(mips_compressed_mark_labels): ... this. Handle microMIPS ASE.
(gpr_mod_mask): New function.
(gpr_read_mask, gpr_write_mask): Handle microMIPS ASE.
(fpr_read_mask, fpr_write_mask): Likewise.
(insns_between, nops_for_vr4130, nops_for_insn): Likewise.
(fix_loongson2f_nop, fix_loongson2f_jump): Likewise.
(MICROMIPS_LABEL_CHAR): New macro.
(micromips_target_label, micromips_target_name): New variables.
(micromips_label_name, micromips_label_expr): New functions.
(micromips_label_inc, micromips_add_label): Likewise.
(mips_label_is_local): Likewise.
(micromips_map_reloc): Likewise.
(can_swap_branch_p): Handle microMIPS ASE.
(append_insn): Add expansionp argument. Handle microMIPS ASE.
(start_noreorder, end_noreorder): Handle microMIPS ASE.
(macro_start, macro_warning, macro_end): Likewise.
(brk_fmt, cop12_fmt, jalr_fmt, lui_fmt): New variables.
(mem12_fmt, mfhl_fmt, shft_fmt, trap_fmt): Likewise.
(BRK_FMT, COP12_FMT, JALR_FMT, LUI_FMT): New macros.
(MEM12_FMT, MFHL_FMT, SHFT_FMT, TRAP_FMT): Likewise.
(macro_build): Handle microMIPS ASE. Update for append_insn
interface change.
(mips16_macro_build): Update for append_insn interface change.
(macro_build_jalr): Handle microMIPS ASE.
(macro_build_lui): Likewise. Simplify.
(load_register): Handle microMIPS ASE.
(load_address): Likewise.
(move_register): Likewise.
(macro_build_branch_likely): New function.
(macro_build_branch_ccl): Likewise.
(macro_build_branch_rs): Likewise.
(macro_build_branch_rsrt): Likewise.
(macro): Handle microMIPS ASE.
(validate_micromips_insn): New function.
(expr_const_in_range): Likewise.
(mips_ip): Handle microMIPS ASE.
(options): Add OPTION_MICROMIPS and OPTION_NO_MICROMIPS.
(md_longopts): Add mmicromips and mno-micromips.
(md_parse_option): Handle OPTION_MICROMIPS and
OPTION_NO_MICROMIPS.
(mips_after_parse_args): Handle microMIPS ASE.
(md_pcrel_from): Handle microMIPS relocations.
(mips_force_relocation): Likewise.
(md_apply_fix): Likewise.
(mips_align): Handle microMIPS ASE.
(s_mipsset): Likewise.
(s_cpload, s_cpsetup, s_cpreturn): Use relocation wrappers.
(s_dtprel_internal): Likewise.
(s_gpword, s_gpdword): Likewise.
(s_insn): Handle microMIPS ASE.
(s_mips_stab): Likewise.
(relaxed_micromips_32bit_branch_length): New function.
(relaxed_micromips_16bit_branch_length): New function.
(md_estimate_size_before_relax): Handle microMIPS ASE.
(mips_fix_adjustable): Likewise.
(tc_gen_reloc): Handle microMIPS relocations.
(mips_relax_frag): Handle microMIPS ASE.
(md_convert_frag): Likewise.
(mips_frob_file_after_relocs): Likewise.
(mips_elf_final_processing): Likewise.
(mips_nop_opcode): Likewise.
(mips_handle_align): Likewise.
(md_show_usage): Handle microMIPS options.
* symbols.c (TC_LABEL_IS_LOCAL): New macro.
(S_IS_LOCAL): Add a TC_LABEL_IS_LOCAL check.
* doc/as.texinfo (Target MIPS options): Add -mmicromips and
-mno-micromips.
(-mmicromips, -mno-micromips): New options.
* doc/c-mips.texi (-mmicromips, -mno-micromips): New options.
(MIPS ISA): Document .set micromips and .set nomicromips.
(MIPS insn): Update for microMIPS support.
gas/testsuite/
2011-02-25 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
* gas/mips/micromips.d: New test.
* gas/mips/micromips-branch-delay.d: Likewise.
* gas/mips/micromips-branch-relax.d: Likewise.
* gas/mips/micromips-branch-relax-pic.d: Likewise.
* gas/mips/micromips-size-1.d: Likewise.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New stderr output.
* gas/mips/micromips-branch-delay.l: Likewise.
* gas/mips/micromips-branch-relax.l: Likewise.
* gas/mips/micromips-branch-relax-pic.l: Likewise.
* gas/mips/micromips-size-0.l: New list test.
* gas/mips/micromips-size-1.l: New stderr output.
* gas/mips/micromips.s: New test source.
* gas/mips/micromips-branch-delay.s: Likewise.
* gas/mips/micromips-branch-relax.s: Likewise.
* gas/mips/micromips-size-0.s: Likewise.
* gas/mips/micromips-size-1.s: Likewise.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/dli.s: Use .p2align.
* gas/mips/elf_ase_micromips.d: New test.
* gas/mips/elf_ase_micromips-2.d: Likewise.
* gas/mips/micromips@abs.d: Likewise.
* gas/mips/micromips@add.d: Likewise.
* gas/mips/micromips@alnv_ps-swap.d: Likewise.
* gas/mips/micromips@and.d: Likewise.
* gas/mips/micromips@beq.d: Likewise.
* gas/mips/micromips@bge.d: Likewise.
* gas/mips/micromips@bgeu.d: Likewise.
* gas/mips/micromips@blt.d: Likewise.
* gas/mips/micromips@bltu.d: Likewise.
* gas/mips/micromips@branch-likely.d: Likewise.
* gas/mips/micromips@branch-misc-1.d: Likewise.
* gas/mips/micromips@branch-misc-2-64.d: Likewise.
* gas/mips/micromips@branch-misc-2.d: Likewise.
* gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
* gas/mips/micromips@branch-misc-2pic.d: Likewise.
* gas/mips/micromips@branch-misc-4-64.d: Likewise.
* gas/mips/micromips@branch-misc-4.d: Likewise.
* gas/mips/micromips@branch-self.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@daddi.d: Likewise.
* gas/mips/micromips@dli.d: Likewise.
* gas/mips/micromips@elf-jal.d: Likewise.
* gas/mips/micromips@elf-rel2.d: Likewise.
* gas/mips/micromips@elfel-rel2.d: Likewise.
* gas/mips/micromips@elf-rel4.d: Likewise.
* gas/mips/micromips@jal-svr4pic.d: Likewise.
* gas/mips/micromips@jal-svr4pic-noreorder.d: Likewise.
* gas/mips/micromips@lb-svr4pic-ilocks.d: Likewise.
* gas/mips/micromips@li.d: Likewise.
* gas/mips/micromips@loc-swap-dis.d: Likewise.
* gas/mips/micromips@loc-swap.d: Likewise.
* gas/mips/micromips@mips1-fp.d: Likewise.
* gas/mips/micromips@mips32-cp2.d: Likewise.
* gas/mips/micromips@mips32-imm.d: Likewise.
* gas/mips/micromips@mips32-sf32.d: Likewise.
* gas/mips/micromips@mips32.d: Likewise.
* gas/mips/micromips@mips32r2-cp2.d: Likewise.
* gas/mips/micromips@mips32r2-fp32.d: Likewise.
* gas/mips/micromips@mips32r2-sync.d: Likewise.
* gas/mips/micromips@mips32r2.d: Likewise.
* gas/mips/micromips@mips4-branch-likely.d: Likewise.
* gas/mips/micromips@mips4-fp.d: Likewise.
* gas/mips/micromips@mips4.d: Likewise.
* gas/mips/micromips@mips5.d: Likewise.
* gas/mips/micromips@mips64-cp2.d: Likewise.
* gas/mips/micromips@mips64.d: Likewise.
* gas/mips/micromips@mips64r2.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips@relax-at.d: Likewise.
* gas/mips/micromips@relax.d: Likewise.
* gas/mips/micromips@rol-hw.d: Likewise.
* gas/mips/micromips@uld2-eb.d: Likewise.
* gas/mips/micromips@uld2-el.d: Likewise.
* gas/mips/micromips@ulh2-eb.d: Likewise.
* gas/mips/micromips@ulh2-el.d: Likewise.
* gas/mips/micromips@ulw2-eb-ilocks.d: Likewise.
* gas/mips/micromips@ulw2-el-ilocks.d: Likewise.
* gas/mips/cache.d: Likewise.
* gas/mips/daddi.d: Likewise.
* gas/mips/mips32-imm.d: Likewise.
* gas/mips/pref.d: Likewise.
* gas/mips/elf-rel27.d: Handle microMIPS ASE.
* gas/mips/l_d.d: Likewise.
* gas/mips/l_d-n32.d: Likewise.
* gas/mips/l_d-n64.d: Likewise.
* gas/mips/ld.d: Likewise.
* gas/mips/ld-n32.d: Likewise.
* gas/mips/ld-n64.d: Likewise.
* gas/mips/s_d.d: Likewise.
* gas/mips/s_d-n32.d: Likewise.
* gas/mips/s_d-n64.d: Likewise.
* gas/mips/sd.d: Likewise.
* gas/mips/sd-n32.d: Likewise.
* gas/mips/sd-n64.d: Likewise.
* gas/mips/mips32.d: Update immediates.
* gas/mips/micromips@mips32-cp2.s: New test source.
* gas/mips/micromips@mips32-imm.s: Likewise.
* gas/mips/micromips@mips32r2-cp2.s: Likewise.
* gas/mips/micromips@mips64-cp2.s: Likewise.
* gas/mips/cache.s: Likewise.
* gas/mips/daddi.s: Likewise.
* gas/mips/mips32-imm.s: Likewise.
* gas/mips/elf-rel4.s: Handle microMIPS ASE.
* gas/mips/lb-pic.s: Likewise.
* gas/mips/ld.s: Likewise.
* gas/mips/mips32.s: Likewise.
* gas/mips/mips.exp: Add the micromips arch. Exclude mips16e
from micromips. Run mips32-imm.
* gas/mips/jal-mask-11.d: New test.
* gas/mips/jal-mask-12.d: Likewise.
* gas/mips/micromips@jal-mask-11.d: Likewise.
* gas/mips/jal-mask-1.s: Source for the new tests.
* gas/mips/jal-mask-21.d: New test.
* gas/mips/jal-mask-22.d: Likewise.
* gas/mips/micromips@jal-mask-12.d: Likewise.
* gas/mips/jal-mask-2.s: Source for the new tests.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/mips16-e.d: Add --special-syms to `objdump'.
* gas/mips/tmips16-e.d: Likewise.
* gas/mips/mipsel16-e.d: Likewise.
* gas/mips/tmipsel16-e.d: Likewise.
* gas/mips/and.s: Adjust padding.
* gas/mips/beq.s: Likewise.
* gas/mips/bge.s: Likewise.
* gas/mips/bgeu.s: Likewise.
* gas/mips/blt.s: Likewise.
* gas/mips/bltu.s: Likewise.
* gas/mips/branch-misc-2.s: Likewise.
* gas/mips/jal.s: Likewise.
* gas/mips/li.s: Likewise.
* gas/mips/mips4.s: Likewise.
* gas/mips/mips4-fp.s: Likewise.
* gas/mips/relax.s: Likewise.
* gas/mips/and.d: Update accordingly.
* gas/mips/elf-jal.d: Likewise.
* gas/mips/jal.d: Likewise.
* gas/mips/li.d: Likewise.
* gas/mips/relax-at.d: Likewise.
* gas/mips/relax.d: Likewise.
include/elf/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (R_MICROMIPS_min): New relocations.
(R_MICROMIPS_26_S1): Likewise.
(R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise.
(R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise.
(R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise.
(R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise.
(R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise.
(R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise.
(R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise.
(R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise.
(R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise.
(R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise.
(R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise.
(R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise.
(R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise.
(R_MICROMIPS_TLS_GOTTPREL): Likewise.
(R_MICROMIPS_TLS_TPREL_HI16): Likewise.
(R_MICROMIPS_TLS_TPREL_LO16): Likewise.
(R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise.
(R_MICROMIPS_max): Likewise.
(EF_MIPS_ARCH_ASE_MICROMIPS): New macro.
(STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise.
(ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise.
(STO_MICROMIPS): Likewise.
(ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise.
(ELF_ST_IS_COMPRESSED): Likewise.
(STO_MIPS_PLT, STO_MIPS_PIC): Rework.
(ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise.
(STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise.
include/opcode/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
(OP_MASK_CODE10, OP_SH_CODE10): Likewise.
(OP_MASK_TRAP, OP_SH_TRAP): Likewise.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
(OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
(OP_MASK_RS3, OP_SH_RS3): Likewise.
(OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
(OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
(OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
(OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
(OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
(OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
(OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
(OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
(OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
(OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
(OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
(OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
(OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
(OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
(INSN_WRITE_GPR_S): New macro.
(INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
(INSN2_READ_FPR_D): Likewise.
(INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
(INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
(INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
(INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
(INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
(CPU_MICROMIPS): New macro.
(M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
(M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
(M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
(M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
(M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
(M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
(M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
(M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
(M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
(M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
(M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
(M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
(M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
(MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
(MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
(MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
(MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
(MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
(MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
(MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
(MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
(MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
(MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
(MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
(MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
(MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
(MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
(MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
(MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
(MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
(MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
(MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
(MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
(MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
(MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
(MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
(MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
(MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
(MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
(MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
(MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
(MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
(MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
(MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
(MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
(MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
(MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
(MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
(MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
(MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
(MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
(MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
(MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
(MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
(MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
(MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
(MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
(MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
(MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
(MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
(MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
(MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
(MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
(MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
(MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
(MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
(MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
(MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
(MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
(MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
(MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
(MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
(MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
(MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
(MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
(MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
(MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
(MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
(MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
(MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
(MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
(MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
(MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
(MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
(MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
(MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
(MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
(micromips_opcodes): New declaration.
(bfd_micromips_num_opcodes): Likewise.
ld/testsuite/
2011-02-25 Catherine Moore <clm@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* lib/ld-lib.exp (run_dump_test): Support distinct assembler
flags for the same source named multiple times.
* ld-mips-elf/jalx-1.s: New test source.
* ld-mips-elf/jalx-1.d: New test output.
* ld-mips-elf/jalx-1.ld: New test linker script.
* ld-mips-elf/jalx-2-main.s: New test source.
* ld-mips-elf/jalx-2-ex.s: Likewise.
* ld-mips-elf/jalx-2-printf.s: Likewise.
* ld-mips-elf/jalx-2.dd: New test output.
* ld-mips-elf/jalx-2.ld: New test linker script.
* ld-mips-elf/mips16-and-micromips.d: New test.
* ld-mips-elf/mips-elf.exp: Run the new tests
opcodes/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* micromips-opc.c: New file.
* mips-dis.c (micromips_to_32_reg_b_map): New array.
(micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): Likewise.
(micromips_ase): New variable.
(is_micromips): New function.
(set_default_mips_dis_options): Handle microMIPS ASE.
(print_insn_micromips): New function.
(is_compressed_mode_p): Likewise.
(_print_insn_mips): Handle microMIPS instructions.
* Makefile.am (CFILES): Add micromips-opc.c.
* configure.in (bfd_mips_arch): Add micromips-opc.lo.
* Makefile.in: Regenerate.
* configure: Regenerate.
* mips-dis.c (micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_n_map): New macro.
|
|
|
|
2010-12-14 Mingjie Xing <mingjie.xing@gmail.com>
* mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
(OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
(INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
opcodes/
2010-12-14 Mingjie Xing <mingjie.xing@gmail.com>
* mips-opc.c (WR_z, WR_Z, RD_z, RD_Z, RD_d): Define.
(mips_builtin_opcodes): Add loongson3a specific instructions.
* mips-dis.c (print_insn_args): Handle the new arguments +a|b|c|z|Z.
gas/
2010-12-14 Mingjie Xing <mingjie.xing@gmail.com>
* config/tc-mips.c (insn_uses_reg): Handle the new flags
INSN2_READ_FPR_Z, INSN2_READ_GPR_D and INSN2_READ_GPR_Z.
(append_insn): Handle delay-slot filling for the new flags.
(validate_mips_insn): Handle the new arguments +a|b|c|z|Z.
(mips_ip): Handle the new arguments +a|b|c|z|Z.
gas/testsuite/
2010-12-14 Mingjie Xing <mingjie.xing@gmail.com>
* gas/mips/loongson-3a-2.s, gas/mips/loongson-3a-2.d,
gas/mips/loongson-3a-3.s, gas/mips/loongson-3a-3.d: New tests.
* gas/mips/mips.exp: Run them.
|
|
* archures.c (bfd_mach_mips_loongson_3a): Defined.
* bfd-in2.h (bfd_mach_mips_loongson_3a): Defined.
* cpu-mips.c (I_loongson_3a): New add.
(arch_info_struct): Add loongson_3a.
* elfxx-mips.c (_bfd_elf_mips_mach): Add loongson_3a.
(mips_set_isa_flags): Add loongson_3a.
(mips_mach_extensions): Add loongson_3a in MIPS64 extensions.
binutils/
* readelf.c (get_machine_flags): Add loongson-3a.
gas/
* config/tc-mips.c (mips_cpu_info_table): Add loongson3a in MIPS 64.
* doc/c-mips.texi (MIPS cpu): Add loongson3a.
include/
* elf/mips.h (E_MIPS_MACH_LS3A): Defined.
* opcode/mips.h (INSN_LOONGSON_3A): Defined.
(CPU_LOONGSON_3A): Defined.
(OPCODE_IS_MEMBER): Add LOONGSON_3A.
opcodes/
* mips-dis.c (mips_arch_choices): Add loongson3a.
* mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
(mips_builtin_opcodes): Modify some instructions' membership from
IL2F to IL2F|IL3A, since these instructions are supported by Loongson_3A.
|
|
determination.
|
|
* config/tc-mips.c (nops_for_insn_or_target): Replace
MIPS16_INSN_BRANCH with MIPS16_INSN_UNCOND_BRANCH and
MIPS16_INSN_COND_BRANCH.
include/opcode/
* mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
(MIPS16_INSN_BRANCH): Rename to...
(MIPS16_INSN_COND_BRANCH): ... this.
opcodes/
* mips-dis.c (print_mips16_insn_arg): Remove branch instruction
type and delay slot determination.
(print_insn_mips16): Extend branch instruction type and delay
slot determination to cover all instructions.
* mips16-opc.c (BR): Remove macro.
(UBR, CBR): New macros.
(mips16_opcodes): Update branch annotation for "b", "beqz",
"bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
and "jrc".
|
|
* config/tc-mips.c (is_opcode_valid): Remove expansionp.
(macro_build): Change invocation of is_opcode_valid.
(mips_ip): Likewise.
gas/testsuite/
* gas/mips/mips-no-jalx.l: Delete.
* gas/mips/mips-no-jalx.s: Delete.
* gas/mips/mips-jalx-2.d: New.
* gas/mips/mips-jalx-2.s: New.
* gas/mips/mips.exp (mips-jalx-2): Run new test.
(mips-no-jalx): Remove deleted test.
include/
* opcode/mips.h (INSN_MIPS16): Remove.
opcodes/
* mips-dis.c (mips_arch): Remove INSN_MIPS16.
* mips-opc.c (I16): Remove.
(mips_builtin_op): Reclassify jalx.
|
|
|
|
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* aoutx.h (NAME (aout, machine_type)): Handle bfd_mach_mips_xlr.
* archures.c (bfd_mach_mips_xlr): Define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_xlr): Define.
(arch_info_struct): Add XLR entry.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_XLR.
(mips_set_isa_flags): Handle bfd_mach_mips_xlr
(mips_mach_extensions): Add XLR entry.
binutils:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* readelf.c (get_machine_flags): Handle E_MIPS_MACH_XLR.
gas:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* config/tc-mips.c (macro): Handle M_MSGSND, M_MSGLD, M_MSGLD_T,
M_MSGWAIT and M_MSGWAIT_T.
(mips_cpu_info_table): Add XLR entry.
* doc/c-mips.texi (-march): Document xlr.
gas/testsuite:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* gas/mips/mips.exp (xlr): New architecture.
(xlr-ext): Run test.
* gas/mips/xlr-ext.d, gas/mips/xlr-ext.s: New.
include/elf:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips.h (E_MIPS_MACH_XLR): Define.
include/opcode:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips.h (INSN_XLR): Define.
(INSN_CHIP_MASK): Update.
(CPU_XLR): Define.
(OPCODE_IS_MEMBER): Update.
(M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
opcodes:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips-dis.c (mips_cp0_names_xlr, mips_cp0sel_names_xlr): Define.
(mips_arch_choices): Add XLR entry.
* mips-opc.c (XLR): Define.
(mips_builtin_opcodes): Add XLR instructions.
|
|
bfd_mach_mips16000.
* archures.c (bfd_architecture): Add .#defines for bfd_mach_mips14000,
bfd_mach_mips16000.
* bfd-in2.h: Regenerate.
* cpu-mips.c: Add enums I_mips14000, I_mips16000.
(arch_info_struct): Add refs to R14000, R16000.
* elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips14000,
bfd_mach_mips16000.
(mips_mach_extensions): Map R14000, R16000 to R10000.
* config/tc-mips.c (hilo_interlocks): Handle CPU_R14000, CPU_R16000.
(mips_cpu_info_table): Add r14000, r16000.
* doc/c-mips.texi: Add entries for 14000, 16000.
* mips-dis.c (mips_arch_choices): Add r14000, r16000.
* mips.h: Define CPU_R14000, CPU_R16000.
(OPCODE_IS_MEMBER): Include R14000, R16000 in test.
|
|
* mips-opc.c (synciobdma, syncs, syncw, syncws): Move these
before sync.
(sync): New instruction with 5-bit sync type.
* mips-dis.c (print_insn_args: Add case '1' to print 5-bit values.
|
|
* mips.h (ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): New macros.
bfd/
* elfxx-mips.c (mips_elf_check_mips16_stubs): Use ELF_ST_IS_MIPS16.
(mips_elf_calculate_relocation): Likewise.
(_bfd_mips_elf_add_symbol_hook): Likewise.
(_bfd_mips_elf_finish_dynamic_symbol): Likewise.
(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
opcodes/
* mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
gas/
* config/tc-mips.c (mips16_mark_labels): Use ELF_ST_SET_MIPS16.
(mips_fix_adjustable): Likewise.
(mips_frob_file_after_relocs): Likewise.
gas/testsuite/
* gas/mips/mips16-vis-1.d, gas/mips/mips16-vis-1.s: New tests.
* gas/mips/mips.exp: Run them.
|
|
* syms.c (BSF_SYNTHETIC): New flag.
* elf.c (_bfd_elf_get_synthetic_symtab): Set it.
* elf32-ppc.c (ppc_elf_get_synthetic_symtab): Likewise.
* elf64-ppc.c (ppc64_elf_get_synthetic_symtab): Likewise.
* bfd-in.h (bfd_asymbol_flavour): Return bfd_target_unknown_flavour
for synthetic symbols.
* bfd-in2.h: Regenerate.
opcodes/
* mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
for ELF symbols.
|
|
(OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
opcodes/
* mips-dis.c (print_insn_args): Handle field descriptor +Q.
* mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
seqi, sne and snei.
gas/
* config/tc-mips.c (validate_mips_insn): Handle field descriptor +Q.
(mips_ip): Likewise.
(macro_build): Likewise.
(CPU_HAS_SEQ): New macro.
(macro2) <M_SEQ_I, M_SNE_I>: Use it. Emit seq/sne and seqi/snei.
gas/testsuite/
* gas/mips/octeon.s, gas/mips/octeon.d: Add tests for seq* and sne*.
* gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: Add tests for seqi
and snei.
|
|
* mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
Update comment before MIPS16 field descriptors to mention MIPS16.
(OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
BBIT.
(OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
New bit masks and shift counts for cins and exts.
gas/
* config/tc-mips.c (validate_mips_insn): Handle field descriptors
+x, +X, +p, +P, +s, +S.
(mips_ip): Likewise.
opcodes/
* mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
+s, +S.
* mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
syncw, syncws, vm3mulu, vm0 and vmulu.
gas/testsuite/
* gas/mips/octeon.s, gas/mips/octeon.d: Add tests for baddu,
bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, syncw,
syncws, vm3mulu, vm0 and vmulu.
* gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: New test.
* gas/mips/mips.exp: Run it. Run octeon test with
run_dump_test_arches.
|
|
(mips_arch_choices): Add Octeon.
* mips-opc.c: Update copyright.
(IOCT): New macro.
(mips_builtin_opcodes): Add Octeon instruction synciobdma.
|
|
* archures.c (bfd_mach_mips_loongson_2e): New.
(bfd_mach_mips_loongson_2f): New.
* bfd-in2.h (bfd_mach_mips_loongson_2e): New.
(bfd_mach_mips_loongson_2f): New.
* cpu-mips.c: Add I_loongson_2e and I_loongson_2f to
anonymous enum.
(arch_info_struct): Add Loongson-2E and Loongson-2F entries.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle Loongson-2E
and Loongson-2F flags.
(mips_set_isa_flags): Likewise.
(mips_mach_extensions): Add Loongson-2E and Loongson-2F
entries.
binutils/
* readelf.c (get_machine_flags): Handle Loongson-2E and -2F
flags.
gas/
* config/tc-mips.c (mips_cpu_info_table): Add loongson2e
and loongson2f entries.
* doc/c-mips.texi: Document -march=loongson{2e,2f} options.
gas/testsuite/
* gas/mips/mips.exp: Add loongson-2e and -2f tests.
* gas/mips/loongson-2e.d: New.
* gas/mips/loongson-2e.s: New.
* gas/mips/loongson-2f.d: New.
* gas/mips/loongson-2f.s: New.
include/elf/
* mips.h (E_MIPS_MACH_LS2E): New.
(E_MIPS_MACH_LS2F): New.
include/opcode/
* mips.h (INSN_LOONGSON_2E): New.
(INSN_LOONGSON_2F): New.
(CPU_LOONGSON_2E): New.
(CPU_LOONGSON_2F): New.
(OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
opcodes/
* mips-dis.c (mips_arch_choices): Add Loongson-2E and -2F
entries.
* mips-opc.c (IL2E): New.
(IL2F): New.
(mips_builtin_opcodes): Add Loongson-2E and -2F instructions.
Allow movz and movn for Loongson-2E and -2F. Add movnz entry.
Move coprocessor encodings to the end of the table. Allow
certain MIPS V .ps instructions on the Loongson-2E and -2F.
|
|
* opcodes/mips-dis.c (mips_cp0_names_r3000): New definition.
(mips_cp0_names_r4000): Likewise.
(mips_arch_choices): Link to the above as appropriate.
gas/testsuite/:
* gas/mips/cp0-names-r3000.d: New test for R3000 CP0 symbolic
disassembly.
* gas/mips/cp0-names-r4000.d: New test for R4000/R4400 symbolic
CP0 disassembly.
* mips/mips.exp: Run the new tests.
|
|
translated properly.
* ia64-gen.c (print_dependency_table): Likewise.
* mips-dis.c (print_insn_args): Likewise.
|
|
|
|
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
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argument and emits the string followed by a comma and then the length of
the string.
(CONST_STRNEQ): New macro. Checks to see if a variable string has a constant
string as its initial characters.
(CONST_STRNCPY): New macro. Copies a constant string to the start of a
variable string.
* bfd-in2.h: Regenerate.
* <remainign files>: Make use of the new macros.
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* config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
(CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
(macro_build): Update comment.
(mips_ip): Allow DSP64 instructions for MIPS64R2.
(mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
CPU_HAS_MDMX.
(mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
MIPS_CPU_ASE_MDMX flags for sb1.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips64-dsp.s, gas/mips/mips64-dsp.d: New DSP64 tests.
* gas/mips/mips.exp: Run DSP64 tests.
[ opcodes/ChangeLog ]
* mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
* mips-opc.c: Add DSP64 instructions.
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2006-05-04 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
* gas/mips/mips.exp: Run mips32-dsp tests only for mips32r2.
* gas/mips/set-arch.d: Adjust according to opcode table changes.
[ include/opcode/ChangeLog ]
2006-05-04 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
David Ung <davidu@mips.com>
* mips.h: Add INSN_SMARTMIPS define.
[ opcodes/ChangeLog ]
2006-05-04 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
David Ung <davidu@mips.com>
* mips-dis.c (mips_arch_choices): Add smartmips instruction
decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
MIPS64R2.
* mips-opc.c: fix random typos in comments.
(INSN_SMARTMIPS): New defines.
(mips_builtin_opcodes): Add paired single support for MIPS32R2.
Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
FP_S and FP_D flags to denote single and double register
accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
for MIPS32R2. Add SmartMIPS instructions. Add two-argument
variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
release 2 ISAs.
* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
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(print_mips16_insn_arg): Force mips16 to odd addresses.
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|
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* config/tc-mips.c (validate_mips_insn): Handling of udi cases.
(mips_immed): New table that records various handling of udi
instruction patterns.
(mips_ip): Adds udi handling.
[ include/opcode/ChangeLog ]
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* mips.h: Defines udi bits and masks. Add description of
characters which may appear in the args field of udi
instructions.
[ opcodes/ChangeLog ]
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* mips-opc.c (mips_builtin_opcodes): Add udi instructions
"udi0" to "udi15".
* mips-dis.c (print_insn_args): Adds udi argument handling.
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|
2006-04-28 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
Nigel Stevens <nigel@mips.com>
* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
names.
[ gas/testsuite/ChangeLog ]
2006-04-28 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
Nigel Stevens <nigel@mips.com>
* gas/mips/cp0sel-names-mips32r2.d,
gas/mips/cp0sel-names-mips64r2.d: Update for MT register names.
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|
(print_insn_mips): Adjust print_insn_args call.
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instructions, use $cc elsewise.
|
|
Map MIPS16 registers to O32 names.
(print_mips16_insn_arg): Use mips16_reg_names.
|
|
instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
save/restore encoding of the args field.
* mips16-opc.c: Add MIPS16e save/restore opcodes.
* mips-dis.c (print_mips16_insn_arg): Handle printing of 'm'/'M'
codes for save/restore.
* config/tc-mips.c (mips16_ip): Add handling of 'm' and 'M' codes
for the MIPS16e save/restore instructions.
* gas/mips/mips.exp: Run new save/restore tests.
* gas/testsuite/gas/mips/mips16e-save.s: New test for generating
different styles of save/restore instructions.
* gas/testsuite/gas/mips/mips16e-save.d: New.
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|
(mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the
bottom to avoid opcode collision with "mftr" and "mttr".
Add MT instructions.
* mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
(print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
formats.
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|
(mips_builtin_opcodes): Add DSP instructions.
* mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2,
mips64, mips64r2.
(print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @
operand formats.
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|
bfd:
* elf32-xtensa.c (vsprint_msg): Add format attribute. Fix
format bugs.
* vms.h (_bfd_vms_debug): Add format attribute.
(_bfd_vms_debug, _bfd_hexdump): Fix typos.
binutils:
* bucomm.h (report): Add format attribute.
* dlltool.c (inform): Likewise.
* dllwrap.c (display, inform, warn): Likewise.
* objdump.c (objdump_sprintf): Likewise.
* readelf.c (error, warn): Likewise. Fix format bugs.
gas:
* config/tc-tic30.c (debug): Add format attribute. Fix format
bugs.
include:
* dis-asm.h (fprintf_ftype): Add format attribute.
opcodes:
* arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
v850-dis.c: Fix format bugs.
* ia64-gen.c (fail, warn): Add format attribute.
* or32-opc.c (debug): Likewise.
|
|
|
|
|
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|
|
* mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
* mips-dis.c: Ditto.
|
|
* mips-dis.c (no_aliases): New disassembly option flag.
(set_default_mips_dis_options): Init no_aliases to zero.
(parse_mips_dis_option): Handle no-aliases option.
(print_insn_mips): Ignore table entries that are aliases
if no_aliases is set.
(print_insn_mips16): Ditto.
* mips-opc.c (mips_builtin_opcodes): Add initializer column for
new pinfo2 member and add INSN_ALIAS initializers as needed. Also
move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
* mips16-opc.c (mips16_opcodes): Ditto.
|
|
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
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* mips.h (CPU_RM7000): New macro.
(OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns.
bfd/
* archures.c (bfd_mach_mips7000): New.
* bfd-in2.h: Regenerated.
* cpu-mips.c (arch_info_struct): Add an entry for mips:7000.
* elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips7000.
(mips_mach_extensions): Add an entry for it.
opcodes/
* mips-dis.c (mips_arch_choices): Add rm7000 and rm9000 entries.
gas/
* config/tc-mips.c (hilo_interlocks): True for CPU_RM7000.
(mips_cpu_info_table): Add rm7000 and rm9000 entries.
gas/testsuite/
* gas/mips/rm7000.[sd]: New test.
* gas/mips/mips.exp: Run it.
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* mips-dis.c (set_default_mips_dis_options): Get BFD from
the disassembler_info's section, rather than from the
disassembler_info's symbols pointer.
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* mips-dis.c (print_mips_disassembler_options): Make 'i' unsigned,
use ARRAY_SIZE in loops.
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* mips-dis.c (print_insn_args): Use position extracted by "+A"
to calculate size for "+B". Redo code for "+C" so it shares
the same style as "+A" and "+B" now do.
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* mips-dis.c: Update copyright years.
(print_insn_arg): Rename to...
(print_insn_args): This, returning void. Process the whole
string of args rather than a single one. Reindent.
(print_insn_mips): Update to match the above.
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2002-12-31 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (validate_mips_insn, mips_ip): Recognize
the "+D" operand, which will be used only by the disassembler.
[ gas/testsuite/ChangeLog ]
2002-12-31 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0sel-names-mips32.d: New test.
* gas/mips/cp0sel-names-mips32r2.d: New test.
* gas/mips/cp0sel-names-mips64.d: New test.
* gas/mips/cp0sel-names-numeric.d: New test.
* gas/mips/cp0sel-names-sb1.d: New test.
* gas/mips/cp0sel-names.s: New test source file.
* gas/mips/mips.exp: Run new tests.
[ include/opcode/ChangeLog ]
2002-12-31 Chris Demetriou <cgd@broadcom.com>
* mips.h: Note that the "+D" operand type name is now used.
[ opcodes/ChangeLog ]
2002-12-31 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0sel_name): New structure.
(mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2)
(mips_cp0sel_names_sb1): New arrays.
(mips_arch_choice): New structure members "cp0sel_names" and
"cp0sel_names_len".
(mips_arch_choices): Add references to new cp0sel_names arrays
as appropriate, and make all existing entries reference
appropriate mips_XXX_names_numeric arrays rather than simply
using NULL.
(mips_cp0sel_names, mips_cp0sel_names_len): New variables.
(lookup_mips_cp0sel_name): New function.
(set_default_mips_dis_options): Set mips_cp0sel_names and
mips_cp0sel_names_len as appropriate. Remove now-unnecessary
checks for NULL register name arrays.
(parse_mips_dis_option): Likewise.
(print_insn_arg): Handle "+D" operand type.
* mips-opc.c (mips_builtin_opcodes): Add new "+D" variants
of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register
names symbolically.
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2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
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