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path: root/opcodes/i386-tbl.h
AgeCommit message (Expand)AuthorFilesLines
2023-01-20x86: re-use insn mnemonic strings as much as possibleJan Beulich1-2211/+1860
2023-01-20x86: move insn mnemonics to a separate tableJan Beulich1-3818/+6144
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-12-16x86: change representation of extension opcodeJan Beulich1-2/+2
2022-12-12x86: further re-work insn/suffix recognition to also cover MOVSXJan Beulich1-937/+889
2022-12-12x86: drop (now) stray IsStringJan Beulich1-13/+13
2022-12-12x86: re-work insn/suffix recognitionJan Beulich1-1275/+1114
2022-12-12x86: generate template sets data at build timeJan Beulich1-0/+2329
2022-12-12x86: drop sentinel from i386_optab[]Jan Beulich1-13/+0
2022-12-12x86: instantiate i386_{op,reg}tab[] in gas instead of in libopcodesJan Beulich1-3/+3
2022-12-03x86: Allow 16-bit register source for LAR and LSLH.J. Lu1-2/+2
2022-12-02x86: also use D for XCHG and TESTJan Beulich1-51/+6
2022-12-01x86: drop No_ldSufJan Beulich1-11149/+11149
2022-12-01x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIXJan Beulich1-2/+2
2022-12-01x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIXJan Beulich1-4/+4
2022-11-30x86: clean up after removal of support for gcc <= 2.8.1Jan Beulich1-32/+2
2022-11-30x86: drop FloatRJan Beulich1-11243/+11183
2022-11-24x86: widen applicability and use of CheckRegSizeJan Beulich1-7/+7
2022-11-24x86: add missing CheckRegSizeJan Beulich1-3/+3
2022-11-24x86: correct handling of LAR and LSLJan Beulich1-2/+32
2022-11-15Add AMD znver4 processor supportTejas Joshi1-3838/+3868
2022-11-14x86: fold special-operand insn attributes into a single enumJan Beulich1-11176/+11176
2022-11-11x86: drop stray IsString from PadLock insnsJan Beulich1-16/+16
2022-11-08Support Intel RAO-INTKong Lingling1-3923/+3983
2022-11-04Support Intel AVX-NE-CONVERTkonglin11-3914/+4064
2022-11-02x86: drop bogus TbyteJan Beulich1-2/+2
2022-11-02Support Intel MSRLISTHu, Lin11-3913/+3939
2022-11-02Support Intel WRMSRNSHu, Lin11-3913/+3926
2022-11-02Support Intel CMPccXADDHaochen Jiang1-3885/+4395
2022-11-02Support Intel AVX-VNNI-INT8Cui,Lili1-390/+492
2022-11-02Support Intel AVX-IFMAHongyu Wang1-3888/+3922
2022-10-31Support Intel PREFETCHICui, Lili1-3887/+3913
2022-10-21Support Intel AMX-FP16Cui,Lili1-3854/+3871
2022-10-20x86: re-work AVX-VNNI supportJan Beulich1-7011/+7011
2022-09-30x86/Intel: restrict suffix derivationJan Beulich1-7318/+7318
2022-08-16x86: template-ize certain vector conversion insnsJan Beulich1-80/+97
2022-08-16x86: template-ize vector packed byte/word integer insnsJan Beulich1-618/+618
2022-08-16x86: re-order AVX512 S/G templatesJan Beulich1-157/+157
2022-08-16x86: template-ize vector packed dword/qword integer insnsJan Beulich1-419/+419
2022-08-16x86: template-ize packed/scalar vector floating point insnsJan Beulich1-3143/+3143
2022-08-09x86-64: adjust MOVQ to/from SReg attributesJan Beulich1-2/+2
2022-08-09x86: adjust MOVSD attributesJan Beulich1-2/+2
2022-08-09x86: fold AVX VGATHERDPD / VPGATHERDQJan Beulich1-40/+6
2022-08-09x86: allow use of broadcast with X/Y/Z-suffixed AVX512-FP16 insnsJan Beulich1-36/+36
2022-08-09x86/Intel: split certain AVX512-FP16 VCVT*2PH templatesJan Beulich1-6/+96
2022-08-03x86: properly mark i386-only insnsJan Beulich1-21/+21
2022-08-03x86: also use D for MOVBEJan Beulich1-16/+1
2022-08-02x86: XOP shift insns don't really allow B suffixJan Beulich1-16/+16
2022-08-01x86: SKINIT with operand needs IgnoreSizeJan Beulich1-1/+1
2022-07-29x86: drop stray NoRex64 from KeyLocker insnsJan Beulich1-3/+3
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