Age | Commit message (Expand) | Author | Files | Lines |
2017-05-22 | x86: Add NOTRACK prefix support | H.J. Lu | 1 | -10643/+10656 |
2017-03-09 | X86: Add pseudo prefixes to control encoding | H.J. Lu | 1 | -0/+91 |
2017-03-09 | Use CpuCET on rdsspq | H.J. Lu | 1 | -1/+1 |
2017-03-06 | Add support for Intel CET instructions | H.J. Lu | 1 | -268/+462 |
2017-02-28 | x86: fix handling of 64-bit operand size VPCMPESTR{I,M} | Jan Beulich | 1 | -6/+120 |
2017-01-12 | Enable Intel AVX512_VPOPCNTDQ instructions | Igor Tsimbalist | 1 | -5209/+5241 |
2017-01-02 | Update year range in copyright notice of all files. | Alan Modra | 1 | -1/+1 |
2016-11-09 | X86: Remove the .s suffix from EVEX vpextrw | H.J. Lu | 1 | -1/+1 |
2016-11-09 | X86: Merge AVX512F vmovq | H.J. Lu | 1 | -73/+9 |
2016-11-02 | Enable Intel AVX512_4VNNIW instructions | Igor Tsimbalist | 1 | -5207/+5321 |
2016-11-02 | Enable Intel AVX512_4FMAPS instructions | Igor Tsimbalist | 1 | -10432/+10584 |
2016-10-21 | X86: Remove pcommit instruction | H.J. Lu | 1 | -5230/+5217 |
2016-08-24 | X86: Add ptwrite instruction | H.J. Lu | 1 | -5199/+5212 |
2016-07-01 | x86: allow suffix-less movzw and 64-bit movzb | Jan Beulich | 1 | -68/+4 |
2016-07-01 | x86: remove stray instruction attributes | Jan Beulich | 1 | -44/+44 |
2016-07-01 | x86/Intel: fix operand checking for MOVSD | Jan Beulich | 1 | -2/+2 |
2016-06-03 | Handle indirect branches for AMD64 and Intel64 | H.J. Lu | 1 | -2/+28 |
2016-05-27 | Update x86 CPU_XXX_FLAGS handling | H.J. Lu | 1 | -5201/+5201 |
2016-05-27 | Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 | H.J. Lu | 1 | -10402/+10402 |
2016-05-27 | Correct CpuMax in i386-opc.h | H.J. Lu | 1 | -2/+2 |
2016-05-10 | Enable Intel RDPID instruction. | Alexander Fomin | 1 | -5199/+5225 |
2016-01-01 | Copyright update for binutils | Alan Modra | 1 | -1/+1 |
2015-12-09 | Implement Intel OSPKE instructions | H.J. Lu | 1 | -5197/+5223 |
2015-06-30 | Add support for monitorx/mwaitx instructions | Amit Pawar | 1 | -5191/+5293 |
2015-06-01 | x86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s} | Jan Beulich | 1 | -6/+6 |
2015-06-01 | x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s} | Jan Beulich | 1 | -0/+132 |
2015-05-18 | Remove Disp32 from AMD64 direct call/jmp | H.J. Lu | 1 | -2/+2 |
2015-05-15 | Support AMD64/Intel ISAs in assembler/disassembler | H.J. Lu | 1 | -5183/+5209 |
2015-05-11 | Remove Disp16|Disp32 from 64-bit direct branches | H.J. Lu | 1 | -3/+16 |
2015-05-11 | Add Intel MCU support to opcodes | H.J. Lu | 1 | -5647/+5647 |
2015-03-17 | Add znver1 processor | Ganesh Gopalasubramanian | 1 | -5181/+5194 |
2015-01-02 | ChangeLog rotatation and copyright year update | Alan Modra | 1 | -1/+1 |
2014-11-17 | Add AVX512VBMI instructions | Ilya Tocar | 1 | -5337/+5565 |
2014-11-17 | Add AVX512IFMA instructions | Ilya Tocar | 1 | -5407/+5521 |
2014-11-17 | Add pcommit instruction | Ilya Tocar | 1 | -5162/+10337 |
2014-11-17 | Add clwb instruction | Ilya Tocar | 1 | -5161/+5173 |
2014-07-22 | Add AVX512DQ instructions and their AVX512VL variants. | Ilya Tocar | 1 | -5726/+8831 |
2014-07-22 | Add support for AVX512BW instructions and their AVX512VL versions. | Ilya Tocar | 1 | -5048/+10952 |
2014-07-22 | Add support for AVX512VL versions of AVX512CD instructions. | Ilya Tocar | 1 | -0/+180 |
2014-07-22 | Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions. | Ilya Tocar | 1 | -4178/+19085 |
2014-04-04 | Add support for Intel SGX instructions | Ilya Tocar | 1 | -3757/+3781 |
2014-03-20 | Fix memory size for gather/scatter instructions | Ilya Tocar | 1 | -8/+8 |
2014-03-05 | Update copyright years | Alan Modra | 1 | -2/+1 |
2014-02-25 | Remove bogus vcvtps2ph variant. | Ilya Tocar | 1 | -18/+0 |
2014-02-21 | Add support for CPUID PREFETCHWT1 | Ilya Tocar | 1 | -3759/+3759 |
2014-02-20 | Change cpu for vptestnmd and vptestnmq instructions. | Ilya Tocar | 1 | -32/+32 |
2014-02-19 | Don't output trailing space | H.J. Lu | 1 | -41582/+41582 |
2014-02-12 | Add clflushopt, xsaves, xsavec, xrstors | Ilya Tocar | 1 | -3752/+3836 |
2013-10-12 | Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcn | H.J. Lu | 1 | -14/+59 |
2013-10-08 | opcodes/ | Jan Beulich | 1 | -17/+17 |