aboutsummaryrefslogtreecommitdiff
path: root/opcodes/i386-tbl.h
AgeCommit message (Expand)AuthorFilesLines
2014-04-04Add support for Intel SGX instructionsIlya Tocar1-3757/+3781
2014-03-20Fix memory size for gather/scatter instructionsIlya Tocar1-8/+8
2014-03-05Update copyright yearsAlan Modra1-2/+1
2014-02-25Remove bogus vcvtps2ph variant.Ilya Tocar1-18/+0
2014-02-21Add support for CPUID PREFETCHWT1Ilya Tocar1-3759/+3759
2014-02-20Change cpu for vptestnmd and vptestnmq instructions.Ilya Tocar1-32/+32
2014-02-19Don't output trailing spaceH.J. Lu1-41582/+41582
2014-02-12Add clflushopt, xsaves, xsavec, xrstorsIlya Tocar1-3752/+3836
2013-10-12Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcnH.J. Lu1-14/+59
2013-10-08opcodes/Jan Beulich1-17/+17
2013-09-30Add Size64 to movq/vmovq with Reg64 operandH.J. Lu1-8/+8
2013-07-26Add Intel AVX-512 supportH.J. Lu1-14774/+37062
2013-07-25Support Intel SHAH.J. Lu1-2690/+2808
2013-07-24Support Intel MPXH.J. Lu1-9818/+9961
2013-07-08Replace Xmmword with Qword on cvttps2piH.J. Lu1-2/+2
2013-04-08gas/testsuite/Jan Beulich1-13/+2
2013-03-02Add RegRex64 to rizH.J. Lu1-4/+4
2013-02-19Implement Intel SMAP instructionsH.J. Lu1-2680/+2702
2013-01-16Add OPERAND_TYPE_IMM32_64H.J. Lu1-1/+1
2012-11-20Fix opcode for 64-bit jecxzH.J. Lu1-1/+1
2012-09-20Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu1-2846/+2846
2012-08-17Add AMD btver1 and btver2 supportH.J. Lu1-1/+1
2012-07-31VMOVNTDQA was both misplaced and improperly tagged as being an AVXJan Beulich1-1/+1
2012-07-16Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu1-2677/+5393
2012-07-02gas/testsuite/Roland McGrath1-1/+1
2012-06-22gas/Roland McGrath1-4/+4
2012-06-22gas/Roland McGrath1-4414/+4414
2012-02-08Implement Intel Transactional Synchronization ExtensionsH.J. Lu1-7078/+7138
2012-01-13Add vmfuncH.J. Lu1-2670/+2680
2011-08-01Add Disp32S to 64bit call.H.J. Lu1-1/+1
2011-07-22Add initial Intel K1OM support.H.J. Lu1-3026/+3026
2011-06-30Fix rorx in BMI2.H.J. Lu1-5/+2
2011-06-10Support AVX Programming Reference (June, 2011).H.J. Lu1-5340/+8170
2011-01-18opcodes/Jan Kratochvil1-2479/+2612
2011-01-05Implement BMI instructions.H.J. Lu1-2476/+2560
2010-10-14Remove CheckRegSize from movq.H.J. Lu1-2/+2
2010-10-14Remove CheckRegSize from instructions with 0, 1 or fixed operands.H.J. Lu1-34/+34
2010-10-14Add CheckRegSize to instructions which require register size check.H.J. Lu1-7417/+7417
2010-08-06Don't generate multi-byte NOPs for i686.H.J. Lu1-4443/+4443
2010-08-06Add Cpu186 to ud1/ud2/ud2a/ud2b.H.J. Lu1-4/+4
2010-08-06Add ud1 to x86.H.J. Lu1-3/+13
2010-07-05Replace rdrnd with rdrand.H.J. Lu1-1/+1
2010-07-01Support AVX Programming Reference (June, 2010)H.J. Lu1-2816/+2944
2010-03-232010-03-22 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop1-53/+1
2010-02-112010-02-10 Quentin Neill <quentin.neill@amd.com>Sebastian Pop1-5543/+5719
2010-01-24Replace "Vex" with "Vex=3" on AVX scalar instructions.H.J. Lu1-208/+208
2010-01-21Add xsave64 and xrstor64.H.J. Lu1-0/+20
2010-01-152010-01-15 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop1-0/+1024
2009-12-19Replace VexNDS, VexNDD and VexLWP with VexVVVV.H.J. Lu1-3492/+3492
2009-12-16Remove ByteOkIntel.H.J. Lu1-3816/+3816
generated by cgit v1.1 at 2024-11-19 08:35:16 +0000