aboutsummaryrefslogtreecommitdiff
path: root/opcodes/i386-tbl.h
AgeCommit message (Expand)AuthorFilesLines
2019-12-04x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich1-3/+3
2019-12-04x86: drop some stray/bogus DefaultSizeJan Beulich1-5/+5
2019-11-14x86: drop redundant SYSCALL/SYSRET templatesJan Beulich1-24/+0
2019-11-14x86: fold individual Jump* attributes into a single Jump oneJan Beulich1-14843/+10922
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich1-26403/+26403
2019-11-14x86: make AnySize an insn attributeJan Beulich1-14458/+14458
2019-11-12x86: fold EsSeg into IsStringJan Beulich1-11187/+11187
2019-11-12x86: eliminate ImmExt abuseJan Beulich1-65/+145
2019-11-12x86: introduce operand type "instance"Jan Beulich1-14078/+14078
2019-11-08i386: Only check suffix in instruction mnemonicH.J. Lu1-2/+2
2019-11-08x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich1-14449/+14449
2019-11-08x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich1-18968/+18968
2019-11-08x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich1-13847/+13847
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich1-13720/+13720
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich1-3913/+3939
2019-11-07x86/Intel: drop IgnoreSize from operand-less MOVSD/CMPSD againJan Beulich1-2/+2
2019-10-30x86: slightly rearrange struct insn_templateJan Beulich1-3912/+3912
2019-10-30x86: drop stray WJan Beulich1-12/+12
2019-10-07x86/Intel: correct MOVSD and CMPSD handlingJan Beulich1-8/+8
2019-09-20x86-64: fix handling of PUSH/POP of segment registerJan Beulich1-2/+28
2019-08-07x86: drop stray FloatMFJan Beulich1-7/+7
2019-07-16x86: make RegMem an opcode modifierJan Beulich1-16396/+20307
2019-07-16x86: fold SReg{2,3}Jan Beulich1-23782/+13834
2019-07-01x86: drop Vec_Imm4Jan Beulich1-9919/+9919
2019-07-01x86: limit ImmExt abuseJan Beulich1-84/+84
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich1-2/+2
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich1-167/+167
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich1-4/+4
2019-07-01x86: add missing pseudo ops for VPCLMULQDQ ISA extensionJan Beulich1-0/+152
2019-07-01x86: drop bogus Disp8MemShift attributesJan Beulich1-3/+3
2019-06-25x86: fix (dis)assembly of certain SSE2 insns in 16-bit modeJan Beulich1-1/+1
2019-06-25x86-64: also optimize ANDQ with immediate fitting in 7 bitsJan Beulich1-1/+1
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-3956/+3994
2019-06-04Add support for Intel ENQCMD[S] instructionsH.J. Lu1-3901/+3965
2019-05-28x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVLH.J. Lu1-2/+2
2019-04-08x86: Consolidate AVX512 BF16 entries in i386-opc.tblH.J. Lu1-260/+22
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-3949/+4305
2019-03-18x86: Optimize EVEX vector load/store instructionsH.J. Lu1-6/+6
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-11-06x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich1-9/+9
2018-11-06x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich1-16/+16
2018-11-06x86: fix various non-LIG templatesJan Beulich1-43/+43
2018-11-06x86: allow {store} to select alternative {,}PEXTRW encodingJan Beulich1-4/+4
2018-11-06x86: add more VexWIGJan Beulich1-142/+142
2018-11-06x86: XOP VPHADD* / VPHSUB* are VEX.W0Jan Beulich1-15/+15
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich1-15568/+11674
2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu1-0/+14
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu1-4/+4
2018-09-17x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu1-8/+8
2018-09-15x86: Set VexW=3 on AVX vrsqrtssH.J. Lu1-1/+1
generated by cgit v1.1 at 2024-11-22 14:43:02 +0000