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path: root/opcodes/i386-tbl.h
AgeCommit message (Expand)AuthorFilesLines
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-4020/+4165
2020-10-16Enhancement for avx-vnni patchCui,Lili1-11177/+11177
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-4292/+4360
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-4274/+4287
2020-10-14x86: Support Intel UINTRLili Cui1-4010/+8085
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu1-730/+730
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu1-6/+6
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-4058/+4106
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-3995/+4141
2020-07-30x86: Add {disp16} pseudo prefixH.J. Lu1-10/+22
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-14093/+14295
2020-07-08x86: FMA4 scalar insns ignore VEX.LJan Beulich1-16/+16
2020-07-02x86: Add SwapSourcesH.J. Lu1-3982/+3982
2020-06-14x86: Correct xsusldtrk mnemonicH.J. Lu1-1/+1
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili1-3980/+4004
2020-04-02Add support for intel SERIALIZE instructionLiliCui1-3979/+3991
2020-03-09x86: use template for AVX512 integer comparison insnsJan Beulich1-32/+32
2020-03-09x86: use template for XOP integer comparison, shift, and rotate insnsJan Beulich1-168/+168
2020-03-09x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich1-3381/+4277
2020-03-09x86: use template for SSE floating point comparison insnsJan Beulich1-144/+144
2020-03-09x86: allow opcode templates to be templatedJan Beulich1-15/+15
2020-03-06x86: reduce amount of various VCVT* templatesJan Beulich1-207/+65
2020-03-06x86: drop/replace IgnoreSizeJan Beulich1-903/+903
2020-03-06x86: don't accept FI{LD,STP,STTP}LL in Intel syntax modeJan Beulich1-6/+6
2020-03-06x86: replace NoRex64 on VEX-encoded insnsJan Beulich1-25/+25
2020-03-06x86: drop Rex64 attributeJan Beulich1-6576/+6576
2020-03-06x86: add missing IgnoreSizeJan Beulich1-18/+30
2020-03-06x86: refine TPAUSE and UMWAITJan Beulich1-6/+38
2020-03-04x86: support VMGEXITJan Beulich1-3929/+3941
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu1-10851/+10851
2020-03-03x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu1-10/+162
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu1-2690/+2690
2020-02-17x86: fold certain VCVT{,U}SI2S{S,D} templatesJan Beulich1-112/+16
2020-02-17x86: fold AddrPrefixOpReg templatesJan Beulich1-177/+29
2020-02-17x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich1-20/+160
2020-02-14x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich1-106/+8
2020-02-12x86: correct VFPCLASSP{S,D} operand size handlingJan Beulich1-2/+34
2020-02-12x86: fold two JMP templatesJan Beulich1-14/+2
2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich1-12/+102
2020-02-11x86: drop ShortForm attributeJan Beulich1-10845/+10845
2020-02-11x86: drop stray ShortForm attributesJan Beulich1-6/+6
2020-02-10x86: Accept Intel64 only instruction by defaultH.J. Lu1-3929/+3929
2020-01-30x86-64: honor vendor specifics for near RETJan Beulich1-2/+26
2020-01-30x86: drop further pointless/bogus DefaultSizeJan Beulich1-8/+8
2020-01-27x86-64: Properly encode and decode movsxdH.J. Lu1-3/+31
2020-01-21x86: improve handling of insns with ambiguous operand sizesJan Beulich1-1/+1
2020-01-21x86: VCVTNEPS2BF16{X,Y} should permit broadcastingJan Beulich1-6/+6
2020-01-17x86: Add {vex} pseudo prefixH.J. Lu1-0/+12
2020-01-16x86: add a few more missing VexWIGJan Beulich1-4/+4
2020-01-16x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit modeJan Beulich1-12/+12
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