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path: root/opcodes/i386-opc.tbl
AgeCommit message (Expand)AuthorFilesLines
2019-11-08i386: Only check suffix in instruction mnemonicH.J. Lu1-2/+2
2019-11-08x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich1-0/+4
2019-11-08x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich1-3/+4
2019-11-08x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich1-0/+4
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich1-0/+2
2019-11-08x86: introduce operand type "class"Jan Beulich1-5/+5
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich1-0/+12
2019-11-07x86/Intel: drop IgnoreSize from operand-less MOVSD/CMPSD againJan Beulich1-2/+2
2019-10-30x86: re-do "shorthand" handlingJan Beulich1-0/+12
2019-10-30x86: drop stray WJan Beulich1-6/+6
2019-10-07x86/Intel: correct MOVSD and CMPSD handlingJan Beulich1-4/+4
2019-09-20x86-64: fix handling of PUSH/POP of segment registerJan Beulich1-2/+4
2019-08-07x86: drop stray FloatMFJan Beulich1-7/+7
2019-07-16x86: make RegMem an opcode modifierJan Beulich1-35/+38
2019-07-16x86: fold SReg{2,3}Jan Beulich1-10/+6
2019-07-01x86: drop Vec_Imm4Jan Beulich1-4/+4
2019-07-01x86: limit ImmExt abuseJan Beulich1-42/+42
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich1-2/+2
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich1-167/+172
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich1-4/+4
2019-07-01x86: add missing pseudo ops for VPCLMULQDQ ISA extensionJan Beulich1-0/+8
2019-07-01x86: drop bogus Disp8MemShift attributesJan Beulich1-3/+3
2019-06-25x86: fix (dis)assembly of certain SSE2 insns in 16-bit modeJan Beulich1-1/+1
2019-06-25x86-64: also optimize ANDQ with immediate fitting in 7 bitsJan Beulich1-1/+1
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-0/+7
2019-06-04Add support for Intel ENQCMD[S] instructionsH.J. Lu1-0/+9
2019-05-28x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVLH.J. Lu1-2/+2
2019-04-08x86: Consolidate AVX512 BF16 entries in i386-opc.tblH.J. Lu1-22/+7
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-0/+30
2019-03-18x86: Optimize EVEX vector load/store instructionsH.J. Lu1-6/+6
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-11-06x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich1-9/+9
2018-11-06x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich1-16/+16
2018-11-06x86: fix various non-LIG templatesJan Beulich1-43/+53
2018-11-06x86: allow {store} to select alternative {,}PEXTRW encodingJan Beulich1-7/+6
2018-11-06x86: add more VexWIGJan Beulich1-143/+143
2018-11-06x86: XOP VPHADD* / VPHSUB* are VEX.W0Jan Beulich1-17/+19
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich1-0/+4
2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu1-0/+1
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu1-4/+4
2018-09-17x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu1-8/+8
2018-09-17x86: Replace VexW=3 with VexWIGH.J. Lu1-468/+470
2018-09-15x86: Set VexW=3 on AVX vrsqrtssH.J. Lu1-1/+1
2018-09-15x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu1-2/+2
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu1-467/+467
2018-09-14x86: fold CRC32 templatesJan Beulich1-6/+2
2018-09-13x86: Remove VexW=1 from WIG VEX movq and vmovqH.J. Lu1-4/+4
2018-09-13i386: Update VexW field for VEX instructionsH.J. Lu1-18/+18
2018-09-13x86: drop bogus IgnoreSize from a few further insnsJan Beulich1-26/+26
2018-09-13x86: drop bogus IgnoreSize from AVX512_4* insnsJan Beulich1-6/+6
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