| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2016-05-27 | Update x86 CPU_XXX_FLAGS handling | H.J. Lu | 1 | -0/+15 |
| 2016-05-27 | Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 | H.J. Lu | 1 | -7/+7 |
| 2016-05-27 | Correct CpuMax in i386-opc.h | H.J. Lu | 1 | -1/+1 |
| 2016-05-10 | Enable Intel RDPID instruction. | Alexander Fomin | 1 | -0/+3 |
| 2016-01-01 | Copyright update for binutils | Alan Modra | 1 | -1/+1 |
| 2015-12-09 | Implement Intel OSPKE instructions | H.J. Lu | 1 | -0/+3 |
| 2015-08-12 | Remove trailing spaces in opcodes | H.J. Lu | 1 | -1/+1 |
| 2015-06-30 | Add support for monitorx/mwaitx instructions | Amit Pawar | 1 | -0/+3 |
| 2015-05-15 | Support AMD64/Intel ISAs in assembler/disassembler | H.J. Lu | 1 | -0/+6 |
| 2015-05-11 | Add Intel MCU support to opcodes | H.J. Lu | 1 | -0/+3 |
| 2015-03-17 | Add znver1 processor | Ganesh Gopalasubramanian | 1 | -0/+3 |
| 2015-01-02 | ChangeLog rotatation and copyright year update | Alan Modra | 1 | -1/+1 |
| 2014-11-17 | Add AVX512VBMI instructions | Ilya Tocar | 1 | -0/+3 |
| 2014-11-17 | Add AVX512IFMA instructions | Ilya Tocar | 1 | -0/+3 |
| 2014-11-17 | Add pcommit instruction | Ilya Tocar | 1 | -0/+3 |
| 2014-11-17 | Add clwb instruction | Ilya Tocar | 1 | -0/+3 |
| 2014-07-22 | Add AVX512DQ instructions and their AVX512VL variants. | Ilya Tocar | 1 | -0/+3 |
| 2014-07-22 | Add support for AVX512BW instructions and their AVX512VL versions. | Ilya Tocar | 1 | -0/+3 |
| 2014-07-22 | Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions. | Ilya Tocar | 1 | -0/+5 |
| 2014-04-04 | Add support for Intel SGX instructions | Ilya Tocar | 1 | -0/+3 |
| 2014-03-05 | Update copyright years | Alan Modra | 1 | -2/+1 |
| 2014-02-21 | Add support for CPUID PREFETCHWT1 | Ilya Tocar | 1 | -0/+3 |
| 2014-02-12 | Add clflushopt, xsaves, xsavec, xrstors | Ilya Tocar | 1 | -0/+9 |
| 2013-07-26 | Add Intel AVX-512 support | H.J. Lu | 1 | -0/+91 |
| 2013-07-25 | Support Intel SHA | H.J. Lu | 1 | -1/+4 |
| 2013-07-24 | Support Intel MPX | H.J. Lu | 1 | -1/+11 |
| 2013-02-19 | Implement Intel SMAP instructions | H.J. Lu | 1 | -0/+3 |
| 2012-09-20 | Replace CpuSSE3 with CpuCX16 for cmpxchg16b | H.J. Lu | 1 | -0/+3 |
| 2012-08-17 | Add AMD btver1 and btver2 support | H.J. Lu | 1 | -1/+1 |
| 2012-07-16 | Implement RDRSEED, ADX and PRFCHW instructions | H.J. Lu | 1 | -0/+9 |
| 2012-06-22 | gas/ | Roland McGrath | 1 | -3/+6 |
| 2012-02-21 | Add HLEPrefixNone/HLEPrefixLock/HLEPrefixAny/HLEPrefixRelease | H.J. Lu | 1 | -0/+4 |
| 2012-02-08 | Implement Intel Transactional Synchronization Extensions | H.J. Lu | 1 | -0/+13 |
| 2012-01-13 | Add vmfunc | H.J. Lu | 1 | -0/+3 |
| 2011-07-22 | Add initial Intel K1OM support. | H.J. Lu | 1 | -0/+3 |
| 2011-06-10 | Support AVX Programming Reference (June, 2011). | H.J. Lu | 1 | -3/+26 |
| 2011-01-17 | Add support for TBM instructions. | Quentin Neill | 1 | -0/+3 |
| 2011-01-05 | Implement BMI instructions. | H.J. Lu | 1 | -0/+3 |
| 2010-10-14 | Add CheckRegSize to instructions which require register size check. | H.J. Lu | 1 | -0/+3 |
| 2010-08-06 | Don't generate multi-byte NOPs for i686. | H.J. Lu | 1 | -0/+3 |
| 2010-08-06 | Fix typos in comments in i386-opc.h. | H.J. Lu | 1 | -6/+6 |
| 2010-07-05 | Fix a typo in comments for CpuFSGSBase. | H.J. Lu | 1 | -1/+1 |
| 2010-07-01 | Support AVX Programming Reference (June, 2010) | H.J. Lu | 1 | -0/+12 |
| 2010-02-11 | Update copyright. | H.J. Lu | 1 | -1/+1 |
| 2010-02-11 | 2010-02-10 Quentin Neill <quentin.neill@amd.com> | Sebastian Pop | 1 | -0/+4 |
| 2010-01-24 | Replace "Vex" with "Vex=3" on AVX scalar instructions. | H.J. Lu | 1 | -2/+4 |
| 2010-01-14 | Replace VEX.DNS with VEX.NDS in comments. | H.J. Lu | 1 | -2/+2 |
| 2009-12-19 | Replace VexNDS, VexNDD and VexLWP with VexVVVV. | H.J. Lu | 1 | -12/+18 |
| 2009-12-16 | Remove ByteOkIntel. | H.J. Lu | 1 | -3/+0 |
| 2009-12-16 | Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode. | H.J. Lu | 1 | -18/+16 |
