| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -2/+2 |
| 2018-10-10 | x86: fold Size{16,32,64} template attributes | Jan Beulich | 1 | -3/+1 |
| 2018-08-11 | x86: Add CpuCMOV and CpuFXSR | H.J. Lu | 1 | -1/+11 |
| 2018-08-03 | x86: drop "mem" operand type attribute | Jan Beulich | 1 | -1/+0 |
| 2018-07-31 | x86: drop CpuVREX | Jan Beulich | 1 | -3/+2 |
| 2018-07-25 | x86: Expand Broadcast to 3 bits | H.J. Lu | 1 | -4/+57 |
| 2018-07-19 | x86: pre-process opcodes table before parsing | Jan Beulich | 1 | -6/+23 |
| 2018-07-11 | x86: drop {,reg16_}inoutportreg variables | Jan Beulich | 1 | -4/+0 |
| 2018-05-30 | Add znver2 support. | Amit Pawar | 1 | -0/+2 |
| 2018-05-07 | Enable Intel MOVDIRI, MOVDIR64B instructions | H.J. Lu | 1 | -0/+10 |
| 2018-05-07 | x86: Replace AddrPrefixOp0 with AddrPrefixOpReg | H.J. Lu | 1 | -1/+1 |
| 2018-04-27 | Revert "Enable Intel MOVDIRI, MOVDIR64B instructions." | Igor Tsimbalist | 1 | -16/+0 |
| 2018-04-26 | Enable Intel MOVDIRI, MOVDIR64B instructions. | Igor Tsimbalist | 1 | -0/+16 |
| 2018-04-26 | x86: CpuXSAVE is a prereq for various other features | Jan Beulich | 1 | -7/+7 |
| 2018-04-26 | x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMask | Jan Beulich | 1 | -15/+6 |
| 2018-04-26 | x86: x87-related adjustments | Jan Beulich | 1 | -3/+3 |
| 2018-04-26 | x86: drop VexImmExt | Jan Beulich | 1 | -1/+0 |
| 2018-04-17 | Enable Intel CLDEMOTE instruction. | Igor Tsimbalist | 1 | -0/+3 |
| 2018-04-11 | Enable Intel WAITPKG instructions. | Igor Tsimbalist | 1 | -0/+3 |
| 2018-03-28 | x86: drop VecESize | Jan Beulich | 1 | -1/+0 |
| 2018-03-08 | x86: Remove support for old (<= 2.8.1) versions of gcc | H.J. Lu | 1 | -1/+0 |
| 2018-03-08 | x86: drop FloatD | Jan Beulich | 1 | -1/+0 |
| 2018-03-03 | opcodes error messages | Alan Modra | 1 | -4/+4 |
| 2018-02-27 | x86: Add -O[2|s] assembler command-line options | H.J. Lu | 1 | -0/+1 |
| 2018-01-23 | Enable Intel PCONFIG instruction. | Igor Tsimbalist | 1 | -0/+3 |
| 2018-01-23 | Enable Intel WBNOINVD instruction. | Igor Tsimbalist | 1 | -0/+3 |
| 2018-01-17 | Replace CET bit with IBT and SHSTK bits. | Igor Tsimbalist | 1 | -3/+10 |
| 2018-01-03 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -2/+2 |
| 2018-01-02 | x86: partial revert of 10c17abdd0 | Jan Beulich | 1 | -0/+4 |
| 2017-12-18 | x86: fold certain AVX and AVX2 templates | Jan Beulich | 1 | -4/+0 |
| 2017-12-18 | x86: fold RegXMM/RegYMM/RegZMM into RegSIMD | Jan Beulich | 1 | -4/+4 |
| 2017-12-18 | x86: drop FloatReg and FloatAcc | Jan Beulich | 1 | -2/+2 |
| 2017-12-18 | x86: replace Reg8, Reg16, Reg32, and Reg64 | Jan Beulich | 1 | -9/+29 |
| 2017-11-30 | x86: derive DispN from BaseIndex | Jan Beulich | 1 | -11/+48 |
| 2017-11-30 | x86: drop Vec_Disp8 | Jan Beulich | 1 | -3/+0 |
| 2017-10-23 | Enable Intel AVX512_BITALG instructions. | Igor Tsimbalist | 1 | -1/+6 |
| 2017-10-23 | Enable Intel AVX512_VNNI instructions. | Igor Tsimbalist | 1 | -1/+6 |
| 2017-10-23 | Enable Intel VPCLMULQDQ instruction. | Igor Tsimbalist | 1 | -0/+3 |
| 2017-10-23 | Enable Intel VAES instructions. | Igor Tsimbalist | 1 | -0/+3 |
| 2017-10-23 | Enable Intel GFNI instructions. | Igor Tsimbalist | 1 | -0/+3 |
| 2017-10-23 | Enable Intel AVX512_VBMI2 instructions. | Igor Tsimbalist | 1 | -1/+6 |
| 2017-05-22 | x86: Add NOTRACK prefix support | H.J. Lu | 1 | -0/+1 |
| 2017-03-09 | X86: Add pseudo prefixes to control encoding | H.J. Lu | 1 | -1/+1 |
| 2017-03-06 | Add support for Intel CET instructions | H.J. Lu | 1 | -0/+3 |
| 2017-01-12 | Enable Intel AVX512_VPOPCNTDQ instructions | Igor Tsimbalist | 1 | -1/+6 |
| 2017-01-02 | Update year range in copyright notice of all files. | Alan Modra | 1 | -2/+2 |
| 2016-11-02 | Enable Intel AVX512_4VNNIW instructions | Igor Tsimbalist | 1 | -1/+6 |
| 2016-11-02 | Enable Intel AVX512_4FMAPS instructions | Igor Tsimbalist | 1 | -1/+7 |
| 2016-10-21 | X86: Remove pcommit instruction | H.J. Lu | 1 | -3/+0 |
| 2016-09-07 | X86: Allow additional ISAs for IAMCU in assembler | H.J. Lu | 1 | -2/+0 |
