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path: root/opcodes/i386-dis.c
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2024-05-22Support APX zero-upperCui, Lili1-0/+29
2024-04-22x86/APX: Add invalid check for APX EVEX.X4.Cui, Lili1-0/+3
2024-04-17Add W table for USER_MSR under MAP4.Hu, Lin11-0/+2
2024-04-09Support {evex} pseudo prefix for decode evex promoted insns without egpr32.Hu, Lin11-40/+72
2024-04-07Support APX NFCui, Lili1-42/+68
2024-04-03x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili1-12/+0
2024-03-15x86/APX: legacy promoted insns can't access %xmm16-%xmm31Jan Beulich1-0/+5
2024-02-09x86/APX: with REX2 map 1 doesn't "chain" to maps 2 or 3Jan Beulich1-7/+5
2024-01-26x86/APX: TILE{RELEASE,ZERO} have no EVEX encodingsJan Beulich1-0/+9
2024-01-26x86/APX: no need to have decode go through x86_64_table[]Jan Beulich1-16/+17
2024-01-19x86/APX: be consistent with insn suffixesJan Beulich1-5/+5
2024-01-19x86: support APX forms of U{RD,WR}MSRJan Beulich1-1/+13
2024-01-07i386: Correct adcx suffix in disassemblerH.J. Lu1-4/+13
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2023-12-28Support APX JMPABS for disassemblerHu, Lin11-2/+35
2023-12-28Support APX pushp/poppCui, Lili1-19/+36
2023-12-28Support APX Push2/Pop2Mo, Zewei1-0/+31
2023-12-28Support APX NDDkonglin11-64/+107
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili1-23/+137
2023-12-28Created an empty EVEX_MAP4_ sub-table for EVEX instructions.Cui, Lili1-0/+1
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili1-90/+167
2023-12-15x86: Intel syntax implies Intel mnemonicsJan Beulich1-5/+6
2023-12-13Make const_1_mode print $1 in AT&T syntaxCui, Lili1-0/+2
2023-10-31Support Intel USER_MSRHu, Lin11-8/+88
2023-08-02Revert "2.41 Release sources"Sam James1-1563/+1070
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-1070/+1563
2023-07-27Support Intel PBNDKBHu, Lin11-0/+14
2023-07-27Support Intel SM4Haochen Jiang1-1/+2
2023-07-27Support Intel SM3Haochen Jiang1-2/+38
2023-07-27Support Intel SHA512Haochen Jiang1-3/+68
2023-07-27Support Intel AVX-VNNI-INT16konglin11-2/+28
2023-07-21x86: adjust disassembly of insns operating on selector valuesJan Beulich1-6/+6
2023-07-21x86: simplify disassembly of LAR/LSLJan Beulich1-14/+2
2023-07-11x86: simplify table-referencing macrosJan Beulich1-17/+15
2023-07-11x86: convert 0FXOP to just XOP in enumerator namesJan Beulich1-304/+304
2023-07-11x86: misc further register-only insns don't need to go through mod_table[]Jan Beulich1-145/+73
2023-07-11x86: various operations on mask registers can avoid going through mod_table[]Jan Beulich1-270/+170
2023-07-11x86: slightly rework handling of some register-only insnsJan Beulich1-61/+52
2023-07-11x86: SIMD shift-by-immediate don't need to go through mod_table[]Jan Beulich1-54/+18
2023-07-11x86: misc further memory-only insns don't need to go through mod_table[]Jan Beulich1-257/+90
2023-07-11x86: {,V}MOVNT* don't need to go through mod_table[]Jan Beulich1-61/+15
2023-07-11x86: fold legacy/VEX {,V}MOV{H,L}* entriesJan Beulich1-66/+32
2023-07-11x86: fold certain legacy/VEX table entriesJan Beulich1-293/+97
2023-07-04x86: flag bad EVEX masking for miscellaneous insnsJan Beulich1-21/+28
2023-07-04x86: flag EVEX masking when destination is GPR(-like)Jan Beulich1-1/+16
2023-07-04x86: flag EVEX.z set when destination is memoryJan Beulich1-0/+7
2023-07-04x86: flag EVEX.z set when destination is a mask registerJan Beulich1-0/+12
2023-07-04x86: re-work EVEX-z-without-masking checkJan Beulich1-10/+8
2023-06-21x86: fix expansion of %XVJan Beulich1-7/+8
2023-05-26x86: fix disassembler build after 1a3b4f90bc5fJan Beulich1-1/+1
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