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path: root/opcodes/i386-dis.c
AgeCommit message (Expand)AuthorFilesLines
2017-07-18Fix spelling typos.Yuri Chornovian1-1/+1
2017-07-05X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctlyBorislav Petkov1-6/+6
2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu1-11/+12
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu1-1/+1
2017-06-21x86: CET v2.0: Update NOTRACK prefixH.J. Lu1-8/+6
2017-06-15i386-dis: Check valid bnd registerH.J. Lu1-0/+10
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi1-1/+1
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-3/+41
2017-03-06Add support for Intel CET instructionsH.J. Lu1-10/+95
2017-02-28x86: fix handling of 64-bit operand size VPCMPESTR{I,M}Jan Beulich1-14/+26
2017-02-24x86: also correctly support TEST opcode aliasesJan Beulich1-2/+2
2017-02-23x86: drop stray VEX opcode 82 referencesJan Beulich1-4/+4
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-0/+2
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-01Fix abort in x86 disassembler.Nick Clifton1-1/+2
2016-11-28X86: Ignore REX_B bit for 32-bit XOP instructionsAmit Pawar1-4/+8
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu1-9/+1
2016-11-08X86: Remove the THREE_BYTE_0F7A entryH.J. Lu1-295/+2
2016-11-07X86: Properly handle bad FPU opcodeH.J. Lu1-18/+23
2016-11-03X86: Reuse opcode 0x80 decoder for opcode 0x82H.J. Lu1-58/+5
2016-11-03X86: Decode opcode 0x82 as opcode 0x80 in 32-bit modeH.J. Lu1-1/+61
2016-11-03X86: Rename REG_82 to REG_83H.J. Lu1-3/+3
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-0/+2
2016-10-21X86: Remove pcommit instructionH.J. Lu1-9/+2
2016-10-20Check invalid mask registersH.J. Lu1-17/+34
2016-10-18Check addr32flag instead of sizeflag for rip/eipH.J. Lu1-2/+2
2016-10-18Remove the remaining SSE5 supportH.J. Lu1-1/+1
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra1-3/+7
2016-09-30Don't assign alt twiceH.J. Lu1-1/+0
2016-08-24X86: Add ptwrite instructionH.J. Lu1-1/+16
2016-06-03Handle indirect branches for AMD64 and Intel64H.J. Lu1-3/+29
2016-05-10Enable Intel RDPID instruction.Alexander Fomin1-1/+1
2016-04-23Skip if size of bfd_vma is smaller than address sizeH.J. Lu1-0/+7
2016-02-15Add parentheses to prevent truncated addressesH.J. Lu1-2/+2
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-09Implement Intel OSPKE instructionsH.J. Lu1-1/+19
2015-08-24Fix the partial disassembly of a broken three byte instruction at the end of ...Jan Stancek1-2/+4
2015-08-21PR binutils/18257: Properly decode x86/Intel mask instructions.Alexander Fomin1-59/+413
2015-07-30Properly disassemble movnti in Intel modeH.J. Lu1-5/+10
2015-07-23Fix ubsan signed integer overflowAlan Modra1-2/+2
2015-06-30Add support for monitorx/mwaitx instructionsAmit Pawar1-2/+22
2015-06-01x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand orderJan Beulich1-0/+7
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu1-5/+40
2015-05-09Ignore 0x66 prefix for call/jmp/jcc in 64-bit modeH.J. Lu1-10/+40
2015-04-23x86: disambiguate disassembly of certain AVX512 insnsJan Beulich1-4/+36
2015-04-15Remove the unused PREFIX_UD_XXXH.J. Lu1-6/+0
2015-04-15Check dp->prefix_requirement insteadH.J. Lu1-5/+1
2015-04-15Handle invalid prefixes for rdrand and rdseedH.J. Lu1-5/+21
2015-04-15Replace mandatory_prefix with prefix_requirementH.J. Lu1-310/+315
2015-04-06x86: Use individual prefix control for each opcode.Ilya Tocar1-1442/+1440
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