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path: root/opcodes/i386-dis-evex.h
AgeCommit message (Expand)AuthorFilesLines
2021-07-22x86: drop vex_scalar_w_dq_modeJan Beulich1-21/+21
2021-07-22x86: drop OP_Mask()Jan Beulich1-11/+11
2021-03-25x86: flag bad S/G insn operand combinationsJan Beulich1-2/+2
2021-03-10x86/Intel: correct AVX512 S/G disassemblyJan Beulich1-4/+4
2021-03-10x86: reuse further VEX entries for EVEXJan Beulich1-10/+10
2021-03-10x86: reuse VEX entries for EVEX vperm{q,pd}Jan Beulich1-2/+2
2021-03-10x86: re-arrange order of decode for various EVEX opcodesJan Beulich1-17/+17
2020-07-14x86: drop Rdq, Rd, and MaskRJan Beulich1-1/+1
2020-07-14x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich1-217/+217
2020-07-14x86: drop further EVEX table entries that can be served by VEX onesJan Beulich1-4/+4
2020-07-06x86: drop EVEX table entries that can be made served by VEX onesJan Beulich1-15/+15
2020-07-06x86: honor VEX.W for VCVT{PH2PS,PS2PH}Jan Beulich1-1/+1
2020-07-06x86: drop EVEX table entries that can be served by VEX onesJan Beulich1-80/+80
2020-06-09x86: utilize X macro in EVEX decodingJan Beulich1-12/+12
2019-06-21i386: Break i386-dis-evex.h into small filesH.J. Lu1-3467/+0
2019-06-19i386: Check vector length for EVEX broadcast instructionsH.J. Lu1-10/+80
2019-06-17i386: Check vector length for vshufXXX/vinsertXXX/vextractXXXH.J. Lu1-12/+96
2019-06-05i386: Check vector length for EVEX vextractfXX and vinsertfXXH.J. Lu1-8/+64
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-1/+13
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-2/+18
2018-11-06x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit modeJan Beulich1-1/+1
2018-11-06x86: correctly handle VMOVD with EVEX.W set outside of 64-bit modeJan Beulich1-12/+2
2018-11-06x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich1-12/+2
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu1-4/+26
2018-09-14x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu1-2/+2
2018-09-14x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu1-4/+4
2018-07-24x86-64: correct AVX512F vcvtsi2s{d,s} handlingJan Beulich1-8/+8
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich1-4/+4
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist1-2/+19
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist1-4/+16
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist1-1/+7
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist1-4/+29
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist1-3/+31
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist1-10/+120
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-1/+12
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu1-1/+1
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-2/+16
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist1-0/+4
2015-07-22Fix memory operand size for vcvtt?ps2u?qq instructionsH.J. Lu1-4/+4
2015-04-23x86: disambiguate disassembly of certain AVX512 insnsJan Beulich1-9/+9
2015-04-06x86: Use individual prefix control for each opcode.Ilya Tocar1-472/+472
2014-11-17Add AVX512VBMI instructionsIlya Tocar1-4/+15
2014-11-17Add AVX512IFMA instructionsIlya Tocar1-2/+14
2014-07-22Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar1-26/+215
2014-07-22Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar1-76/+636
2014-07-08Fix disasm of vmovsd/vmovss with different length values.Ilya Tocar1-2/+2
2014-03-20Fix memory size for gather/scatter instructionsIlya Tocar1-8/+8
2013-08-19Remove PREFIX_EVEX_0F3A3E and PREFIX_EVEX_0F3A3FH.J. Lu1-14/+2
2013-07-26Add Intel AVX-512 supportH.J. Lu1-0/+3115
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