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path: root/opcodes/i386-dis-evex.h
AgeCommit message (Expand)AuthorFilesLines
2023-08-02Revert "2.41 Release sources"Sam James1-30/+30
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-30/+30
2023-07-11x86: misc further register-only insns don't need to go through mod_table[]Jan Beulich1-1/+1
2023-07-11x86: slightly rework handling of some register-only insnsJan Beulich1-1/+1
2023-07-11x86: misc further memory-only insns don't need to go through mod_table[]Jan Beulich1-6/+6
2023-07-11x86: {,V}MOVNT* don't need to go through mod_table[]Jan Beulich1-1/+1
2023-07-11x86: fold legacy/VEX {,V}MOV{H,L}* entriesJan Beulich1-2/+2
2023-07-11x86: fold certain legacy/VEX table entriesJan Beulich1-12/+12
2023-07-04x86: flag bad EVEX masking for miscellaneous insnsJan Beulich1-7/+7
2022-11-02Support Intel AVX-IFMAHongyu Wang1-2/+2
2022-10-24x86: emit {evex} prefix when disassembling ambiguous AVX512VL insnsJan Beulich1-87/+87
2022-10-17x86: fold AVX512-VNNI disassembler entries with AVX-VNNI onesJan Beulich1-2/+2
2022-01-14x86: share yet more VEX table entries with EVEX decodingJan Beulich1-16/+16
2022-01-14x86: consistently use scalar_mode for AVX512-FP16 scalar insnsJan Beulich1-16/+16
2022-01-14x86: reduce AVX512 FP set of insns decoded through vex_w_table[]Jan Beulich1-4/+4
2022-01-14x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]Jan Beulich1-5/+5
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili1-13/+595
2021-07-22x86: drop vex_scalar_w_dq_modeJan Beulich1-21/+21
2021-07-22x86: drop OP_Mask()Jan Beulich1-11/+11
2021-03-25x86: flag bad S/G insn operand combinationsJan Beulich1-2/+2
2021-03-10x86/Intel: correct AVX512 S/G disassemblyJan Beulich1-4/+4
2021-03-10x86: reuse further VEX entries for EVEXJan Beulich1-10/+10
2021-03-10x86: reuse VEX entries for EVEX vperm{q,pd}Jan Beulich1-2/+2
2021-03-10x86: re-arrange order of decode for various EVEX opcodesJan Beulich1-17/+17
2020-07-14x86: drop Rdq, Rd, and MaskRJan Beulich1-1/+1
2020-07-14x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich1-217/+217
2020-07-14x86: drop further EVEX table entries that can be served by VEX onesJan Beulich1-4/+4
2020-07-06x86: drop EVEX table entries that can be made served by VEX onesJan Beulich1-15/+15
2020-07-06x86: honor VEX.W for VCVT{PH2PS,PS2PH}Jan Beulich1-1/+1
2020-07-06x86: drop EVEX table entries that can be served by VEX onesJan Beulich1-80/+80
2020-06-09x86: utilize X macro in EVEX decodingJan Beulich1-12/+12
2019-06-21i386: Break i386-dis-evex.h into small filesH.J. Lu1-3467/+0
2019-06-19i386: Check vector length for EVEX broadcast instructionsH.J. Lu1-10/+80
2019-06-17i386: Check vector length for vshufXXX/vinsertXXX/vextractXXXH.J. Lu1-12/+96
2019-06-05i386: Check vector length for EVEX vextractfXX and vinsertfXXH.J. Lu1-8/+64
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-1/+13
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-2/+18
2018-11-06x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit modeJan Beulich1-1/+1
2018-11-06x86: correctly handle VMOVD with EVEX.W set outside of 64-bit modeJan Beulich1-12/+2
2018-11-06x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich1-12/+2
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu1-4/+26
2018-09-14x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu1-2/+2
2018-09-14x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu1-4/+4
2018-07-24x86-64: correct AVX512F vcvtsi2s{d,s} handlingJan Beulich1-8/+8
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich1-4/+4
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist1-2/+19
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist1-4/+16
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist1-1/+7
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist1-4/+29
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist1-3/+31
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