Age | Commit message (Expand) | Author | Files | Lines |
2024-05-22 | Support APX zero-upper | Cui, Lili | 1 | -18/+18 |
2024-04-09 | Support {evex} pseudo prefix for decode evex promoted insns without egpr32. | Hu, Lin1 | 1 | -2/+2 |
2024-04-07 | Support APX NF | Cui, Lili | 1 | -38/+38 |
2024-04-03 | x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4 | Cui, Lili | 1 | -9/+9 |
2024-01-26 | x86/APX: TILE{RELEASE,ZERO} have no EVEX encodings | Jan Beulich | 1 | -2/+2 |
2024-01-26 | x86/APX: no need to have decode go through x86_64_table[] | Jan Beulich | 1 | -10/+10 |
2023-12-28 | Support APX Push2/Pop2 | Mo, Zewei | 1 | -1/+1 |
2023-12-28 | Support APX NDD | konglin1 | 1 | -62/+62 |
2023-12-28 | Support APX GPR32 with extend evex prefix | Cui, Lili | 1 | -47/+47 |
2023-12-28 | Created an empty EVEX_MAP4_ sub-table for EVEX instructions. | Cui, Lili | 1 | -0/+291 |
2023-08-02 | Revert "2.41 Release sources" | Sam James | 1 | -30/+30 |
2023-08-02 | 2.41 Release sourcesbinutils-2_41-release | Nick Clifton | 1 | -30/+30 |
2023-07-11 | x86: misc further register-only insns don't need to go through mod_table[] | Jan Beulich | 1 | -1/+1 |
2023-07-11 | x86: slightly rework handling of some register-only insns | Jan Beulich | 1 | -1/+1 |
2023-07-11 | x86: misc further memory-only insns don't need to go through mod_table[] | Jan Beulich | 1 | -6/+6 |
2023-07-11 | x86: {,V}MOVNT* don't need to go through mod_table[] | Jan Beulich | 1 | -1/+1 |
2023-07-11 | x86: fold legacy/VEX {,V}MOV{H,L}* entries | Jan Beulich | 1 | -2/+2 |
2023-07-11 | x86: fold certain legacy/VEX table entries | Jan Beulich | 1 | -12/+12 |
2023-07-04 | x86: flag bad EVEX masking for miscellaneous insns | Jan Beulich | 1 | -7/+7 |
2022-11-02 | Support Intel AVX-IFMA | Hongyu Wang | 1 | -2/+2 |
2022-10-24 | x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns | Jan Beulich | 1 | -87/+87 |
2022-10-17 | x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones | Jan Beulich | 1 | -2/+2 |
2022-01-14 | x86: share yet more VEX table entries with EVEX decoding | Jan Beulich | 1 | -16/+16 |
2022-01-14 | x86: consistently use scalar_mode for AVX512-FP16 scalar insns | Jan Beulich | 1 | -16/+16 |
2022-01-14 | x86: reduce AVX512 FP set of insns decoded through vex_w_table[] | Jan Beulich | 1 | -4/+4 |
2022-01-14 | x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[] | Jan Beulich | 1 | -5/+5 |
2021-08-05 | [PATCH 1/2] Enable Intel AVX512_FP16 instructions | Cui,Lili | 1 | -13/+595 |
2021-07-22 | x86: drop vex_scalar_w_dq_mode | Jan Beulich | 1 | -21/+21 |
2021-07-22 | x86: drop OP_Mask() | Jan Beulich | 1 | -11/+11 |
2021-03-25 | x86: flag bad S/G insn operand combinations | Jan Beulich | 1 | -2/+2 |
2021-03-10 | x86/Intel: correct AVX512 S/G disassembly | Jan Beulich | 1 | -4/+4 |
2021-03-10 | x86: reuse further VEX entries for EVEX | Jan Beulich | 1 | -10/+10 |
2021-03-10 | x86: reuse VEX entries for EVEX vperm{q,pd} | Jan Beulich | 1 | -2/+2 |
2021-03-10 | x86: re-arrange order of decode for various EVEX opcodes | Jan Beulich | 1 | -17/+17 |
2020-07-14 | x86: drop Rdq, Rd, and MaskR | Jan Beulich | 1 | -1/+1 |
2020-07-14 | x86: simplify decode of opcodes valid with (embedded) 66 prefix only | Jan Beulich | 1 | -217/+217 |
2020-07-14 | x86: drop further EVEX table entries that can be served by VEX ones | Jan Beulich | 1 | -4/+4 |
2020-07-06 | x86: drop EVEX table entries that can be made served by VEX ones | Jan Beulich | 1 | -15/+15 |
2020-07-06 | x86: honor VEX.W for VCVT{PH2PS,PS2PH} | Jan Beulich | 1 | -1/+1 |
2020-07-06 | x86: drop EVEX table entries that can be served by VEX ones | Jan Beulich | 1 | -80/+80 |
2020-06-09 | x86: utilize X macro in EVEX decoding | Jan Beulich | 1 | -12/+12 |
2019-06-21 | i386: Break i386-dis-evex.h into small files | H.J. Lu | 1 | -3467/+0 |
2019-06-19 | i386: Check vector length for EVEX broadcast instructions | H.J. Lu | 1 | -10/+80 |
2019-06-17 | i386: Check vector length for vshufXXX/vinsertXXX/vextractXXX | H.J. Lu | 1 | -12/+96 |
2019-06-05 | i386: Check vector length for EVEX vextractfXX and vinsertfXX | H.J. Lu | 1 | -8/+64 |
2019-06-04 | Enable Intel AVX512_VP2INTERSECT insn | H.J. Lu | 1 | -1/+13 |
2019-04-05 | x86: Support Intel AVX512 BF16 | Xuepeng Guo | 1 | -2/+18 |
2018-11-06 | x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit mode | Jan Beulich | 1 | -1/+1 |
2018-11-06 | x86: correctly handle VMOVD with EVEX.W set outside of 64-bit mode | Jan Beulich | 1 | -12/+2 |
2018-11-06 | x86: adjust {,E}VEX.W handling for PEXTR* / PINSR* | Jan Beulich | 1 | -12/+2 |