| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2017-04-21 | Fix detection of illegal AArch64 opcodes that resemble LD1R, LD2R, LD3R and L... | Nick Clifton | 1 | -8/+8 |
| 2017-02-24 | [AArch64] Additional SVE instructions | Richard Sandiford | 1 | -96/+230 |
| 2017-02-24 | [AArch64] Add a "compnum" feature | Richard Sandiford | 1 | -6/+8 |
| 2017-01-04 | [AArch64] Add separate feature flag for weaker release consistent load insns | Szabolcs Nagy | 1 | -3/+8 |
| 2017-01-02 | Update year range in copyright notice of all files. | Alan Modra | 1 | -1/+1 |
| 2016-12-13 | [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm field | Renlin Li | 1 | -6/+6 |
| 2016-11-18 | [AArch64] Add ARMv8.3 FCMLA and FCADD instructions | Szabolcs Nagy | 1 | -0/+30 |
| 2016-11-18 | [AArch64] Add ARMv8.3 weaker release consistency load instructions | Szabolcs Nagy | 1 | -0/+3 |
| 2016-11-18 | [AArch64] Add ARMv8.3 javascript floating-point conversion instruction | Szabolcs Nagy | 1 | -0/+10 |
| 2016-11-18 | [AArch64] Add ARMv8.3 combined pointer authentication load instructions | Szabolcs Nagy | 1 | -0/+11 |
| 2016-11-11 | [AArch64] Add ARMv8.3 combined pointer authentication branch instructions | Szabolcs Nagy | 1 | -0/+12 |
| 2016-11-11 | [AArch64] Add ARMv8.3 PACGA instruction | Szabolcs Nagy | 1 | -0/+3 |
| 2016-11-11 | [AArch64] Add ARMv8.3 single source PAC instructions | Szabolcs Nagy | 1 | -0/+18 |
| 2016-11-11 | [AArch64] Add ARMv8.3 instructions which are in the NOP space | Szabolcs Nagy | 1 | -0/+18 |
| 2016-09-30 | [AArch64] PR target/20553, fix opcode mask for SIMD multiply by element | Jiong Wang | 1 | -4/+4 |
| 2016-09-21 | [AArch64][SVE 31/32] Add SVE instructions | Richard Sandiford | 1 | -0/+1269 |
| 2016-09-21 | [AArch64][SVE 29/32] Add new SVE core & FP register operands | Richard Sandiford | 1 | -0/+8 |
| 2016-09-21 | [AArch64][SVE 28/32] Add SVE FP immediate operands | Richard Sandiford | 1 | -0/+8 |
| 2016-09-21 | [AArch64][SVE 27/32] Add SVE integer immediate operands | Richard Sandiford | 1 | -0/+39 |
| 2016-09-21 | [AArch64][SVE 26/32] Add SVE MUL VL addressing modes | Richard Sandiford | 1 | -0/+18 |
| 2016-09-21 | [AArch64][SVE 25/32] Add support for SVE addressing modes | Richard Sandiford | 1 | -1/+88 |
| 2016-09-21 | [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED | Richard Sandiford | 1 | -0/+2 |
| 2016-09-21 | [AArch64][SVE 23/32] Add SVE pattern and prfop operands | Richard Sandiford | 1 | -0/+4 |
| 2016-09-21 | [AArch64][SVE 21/32] Add Zn and Pn registers | Richard Sandiford | 1 | -1/+37 |
| 2016-09-21 | [AArch64][SVE 20/32] Add support for tied operands | Richard Sandiford | 1 | -16/+16 |
| 2016-09-21 | [AArch64][SVE 16/32] Use specific insert/extract methods for fpimm | Richard Sandiford | 1 | -1/+1 |
| 2016-08-23 | [AArch64] Add V8_2_INSN macro | Richard Sandiford | 1 | -2/+4 |
| 2016-08-23 | [AArch64] Make more use of CORE/FP/SIMD_INSN | Richard Sandiford | 1 | -67/+67 |
| 2016-08-23 | [AArch64] Add OP parameter to aarch64-tbl.h macros | Richard Sandiford | 1 | -722/+722 |
| 2016-05-03 | Fix generation of AArhc64 instruction table. | Szabolcs Nagy | 1 | -2/+6 |
| 2016-04-28 | Add support to AArch64 disassembler for verifying instructions. Add verifier... | Nick Clifton | 1 | -1332/+1191 |
| 2016-03-18 | Fix the disassembly of the AArch64's OOR instruction as a MOV instruction. | Nick Clifton | 1 | -1/+1 |
| 2016-01-01 | Copyright update for binutils | Alan Modra | 1 | -1/+1 |
| 2015-12-14 | [AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru... | Matthew Wahab | 1 | -0/+14 |
| 2015-12-14 | [AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions. | Matthew Wahab | 1 | -0/+15 |
| 2015-12-14 | [AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions. | Matthew Wahab | 1 | -0/+16 |
| 2015-12-14 | [AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions. | Matthew Wahab | 1 | -0/+9 |
| 2015-12-14 | [AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions. | Matthew Wahab | 1 | -0/+15 |
| 2015-12-14 | [AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions. | Matthew Wahab | 1 | -0/+8 |
| 2015-12-14 | [AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions. | Matthew Wahab | 1 | -0/+15 |
| 2015-12-14 | [AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions. | Matthew Wahab | 1 | -0/+52 |
| 2015-12-14 | [AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions. | Matthew Wahab | 1 | -0/+65 |
| 2015-12-14 | [AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions. | Matthew Wahab | 1 | -0/+18 |
| 2015-12-14 | [AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions. | Matthew Wahab | 1 | -0/+55 |
| 2015-12-14 | [AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions. | Matthew Wahab | 1 | -0/+3 |
| 2015-12-11 | [AArch64][Patch 5/5] Add instruction PSB CSYNC | Matthew Wahab | 1 | -1/+8 |
| 2015-12-11 | [AArch64][Patch 4/5] Support HINT aliases taking operands. | Matthew Wahab | 1 | -2/+2 |
| 2015-12-10 | [AArch64][PATCH 1/2] Add support for RAS instruction ESB. | Matthew Wahab | 1 | -0/+4 |
| 2015-11-27 | [AArch64][PATCH 3/3] Add floating-point FP16 instructions | Matthew Wahab | 1 | -0/+164 |
| 2015-11-27 | [AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions. | Matthew Wahab | 1 | -0/+3 |
