| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-01-11 | aarch64: Remove support for CSRE | Kyrylo Tkachov | 1 | -7/+0 |
| 2021-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2020-11-16 | aarch64: Extract Condition flag manipulation feature from Armv8.4-A | Przemyslaw Wirkus | 1 | -4/+9 |
| 2020-11-11 | aarch64: Allow LS64 feature with Armv8.6 | Przemyslaw Wirkus | 1 | -1/+1 |
| 2020-11-09 | aarch64: Limit Rt register number for LS64 load/store instructions | Przemyslaw Wirkus | 1 | -4/+5 |
| 2020-11-06 | aarch64: Extract Pointer Authentication feature from Armv8.3-A | Przemyslaw Wirkus | 1 | -33/+38 |
| 2020-11-03 | [PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7 | Przemyslaw Wirkus | 1 | -2/+16 |
| 2020-10-30 | [PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-a | Przemyslaw Wirkus | 1 | -0/+1 |
| 2020-10-28 | aarch64: Add CSR PDEC instruction | Przemyslaw Wirkus | 1 | -0/+8 |
| 2020-10-28 | aarch64: Add WFET instruction for Armv8.7-a | Przemyslaw Wirkus | 1 | -0/+1 |
| 2020-10-28 | aarch64: Add DSB instruction Armv8.7-a variant | Przemyslaw Wirkus | 1 | -0/+5 |
| 2020-10-28 | aarch64: Add basic support for armv8.7-a architecture | Przemyslaw Wirkus | 1 | -0/+3 |
| 2020-09-08 | aarch64: Add support for Armv8-R DFB alias | Alex Coplan | 1 | -0/+6 |
| 2020-04-30 | AArch64: add GAS support for UDF instruction | Alex Coplan | 1 | -0/+3 |
| 2020-04-20 | [AArch64, Binutils] Add missing TSB instruction | Sudakshina Das | 1 | -2/+3 |
| 2020-04-20 | [AArch64, Binutils] Make hint space instructions valid for Armv8-a | Sudakshina Das | 1 | -30/+17 |
| 2020-01-31 | aarch64: Fix MOVPRFX markup for bf16 conversions | Richard Sandiford | 1 | -2/+2 |
| 2020-01-27 | AArch64: Fix cfinv disassembly issues | Tamar Christina | 1 | -1/+8 |
| 2020-01-03 | Arm64: correct address index operands for LD1RO{H,W,D} | Jan Beulich | 1 | -4/+4 |
| 2020-01-03 | Arm64: correct {su,us}dot SIMD encodings | Jan Beulich | 1 | -3/+3 |
| 2020-01-03 | Arm64: correct uzp{1,2} mnemonics | Jan Beulich | 1 | -2/+2 |
| 2020-01-03 | Arm64: correct 64-bit element fmmla encoding | Jan Beulich | 1 | -1/+1 |
| 2020-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2019-12-05 | Arm64: simplify Crypto arch extension handling | Jan Beulich | 1 | -12/+0 |
| 2019-11-11 | Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same register | Jan Beulich | 1 | -2/+2 |
| 2019-11-07 | [gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X] | Matthew Malcomson | 1 | -0/+5 |
| 2019-11-07 | [binutils][aarch64] Matrix Multiply extension enablement [8/X] | Matthew Malcomson | 1 | -0/+74 |
| 2019-11-07 | [binutils][aarch64] Bfloat16 enablement [2/X] | Matthew Malcomson | 1 | -0/+80 |
| 2019-11-07 | [gas][aarch64] Armv8.6-a option [1/X] | Matthew Malcomson | 1 | -0/+3 |
| 2019-10-30 | Modify the ARNM assembler to accept the omission of the immediate argument fo... | Delia Burduv | 1 | -1/+1 |
| 2019-07-02 | [AArch64] Allow MOVPRFX to be used with FMOV | Richard Sandiford | 1 | -1/+1 |
| 2019-07-02 | [AArch64] Add missing C_MAX_ELEM flags for SVE conversions | Richard Sandiford | 1 | -28/+28 |
| 2019-07-01 | [gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES | Matthew Malcomson | 1 | -5/+10 |
| 2019-05-09 | [binutils][aarch64] Add SVE2 instructions. | Matthew Malcomson | 1 | -0/+419 |
| 2019-05-09 | [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand. | Matthew Malcomson | 1 | -0/+3 |
| 2019-05-09 | [binutils][aarch64] New SVE_Zm4_11_INDEX operand. | Matthew Malcomson | 1 | -0/+3 |
| 2019-05-09 | [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand. | Matthew Malcomson | 1 | -2/+5 |
| 2019-05-09 | [binutils][aarch64] New SVE_ADDR_ZX operand. | Matthew Malcomson | 1 | -0/+3 |
| 2019-05-09 | [binutils][aarch64] New SVE_Zm3_11_INDEX operand. | Matthew Malcomson | 1 | -0/+3 |
| 2019-05-09 | [binutils][aarch64] Introduce SVE_IMM_ROT3 operand. | Matthew Malcomson | 1 | -0/+2 |
| 2019-05-09 | [binutils][aarch64] SVE2 feature extension flags. | Matthew Malcomson | 1 | -0/+36 |
| 2019-05-01 | [BINUTILS, AArch64] Enable Transactional Memory Extension | Sudakshina Das | 1 | -0/+18 |
| 2019-04-11 | [BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions | Sudakshina Das | 1 | -9/+12 |
| 2019-04-11 | [BINUTILS, AArch64, 1/2] Add new LDGM/STGM instruction | Sudakshina Das | 1 | -0/+2 |
| 2019-02-07 | AArch64: Add verifier for By elem Single and Double sized instructions. | Tamar Christina | 1 | -8/+10 |
| 2019-01-25 | AArch64: Update encodings for stg, st2g, stzg and st2zg. | Sudi Das | 1 | -10/+10 |
| 2019-01-25 | AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension. | Sudi Das | 1 | -0/+1 |
| 2019-01-25 | AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte... | Sudi Das | 1 | -4/+0 |
| 2019-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2018-12-03 | [aarch64] - Only use MOV for disassembly when shifter op is LSL #0 | Egeyar Bagcioglu | 1 | -1/+1 |
