| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction | Sudakshina Das | 1 | -0/+8 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions | Sudakshina Das | 1 | -0/+10 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A | Sudakshina Das | 1 | -0/+6 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A | Sudakshina Das | 1 | -0/+21 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea... | Sudakshina Das | 1 | -0/+6 |
| 2018-10-03 | AArch64: Mark sve instructions that require MOVPRFX constraints | Tamar Christina | 1 | -231/+234 |
| 2018-07-12 | This patch adds support for the SSBB and PSSBB speculation barrier instructio... | Nick Clifton | 1 | -1/+3 |
| 2018-07-12 | Add remainder of Em16 restrictions for AArch64 gas. | Tamar Christina | 1 | -26/+26 |
| 2018-07-06 | Fix SBO bit in disassembly mask for ldrah on AArch64. | Tamar Christina | 1 | -1/+1 |
| 2018-06-29 | Fix AArch64 encodings for by element instructions. | Tamar Christina | 1 | -22/+24 |
| 2018-06-22 | Correct negs aliasing on AArch64. | Tamar Christina | 1 | -1/+1 |
| 2018-06-08 | Prevent undefined FMOV instructions being accepted by the AArch64 assembler. | Egeyar Bagcioglu | 1 | -2/+16 |
| 2018-05-16 | Fix disassembly mask for vector sdot on AArch64. | Tamar Christina | 1 | -2/+2 |
| 2018-05-15 | Implement Read/Write constraints on system registers on AArch64 | Tamar Christina | 1 | -3/+3 |
| 2018-04-25 | Fix the mask for the sqrdml(a|s)h instructions. | Tamar Christina | 1 | -2/+2 |
| 2018-03-28 | Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R... | Nick Clifton | 1 | -0/+26 |
| 2018-01-09 | Add support for the AArch64's CSDB instruction. | James Greenhalgh | 1 | -0/+1 |
| 2018-01-03 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2017-12-19 | Correct disassembly of dot product instructions. | Tamar Christina | 1 | -2/+2 |
| 2017-11-16 | Add new AArch64 FP16 FM{A|S} instructions. | Tamar Christina | 1 | -2/+2 |
| 2017-11-16 | Correct AArch64 crypto dependencies. | Tamar Christina | 1 | -4/+6 |
| 2017-11-16 | Add assembler and disassembler support for the new Armv8.4-a instructions for... | Tamar Christina | 1 | -1/+60 |
| 2017-11-09 | Add the operand encoding types for the new Armv8.2-a back-ported instructions... | Tamar Christina | 1 | -0/+90 |
| 2017-11-09 | Adds the new Fields and Operand types for the new instructions in Armv8.4-a. | Tamar Christina | 1 | -2/+10 |
| 2017-11-09 | Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options... | Tamar Christina | 1 | -0/+27 |
| 2017-11-08 | Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio... | Nick Clifton | 1 | -17/+28 |
| 2017-06-28 | [AArch64] Add dot product support for AArch64 to binutils | Tamar Christina | 1 | -0/+24 |
| 2017-04-21 | Fix detection of illegal AArch64 opcodes that resemble LD1R, LD2R, LD3R and L... | Nick Clifton | 1 | -8/+8 |
| 2017-02-24 | [AArch64] Additional SVE instructions | Richard Sandiford | 1 | -96/+230 |
| 2017-02-24 | [AArch64] Add a "compnum" feature | Richard Sandiford | 1 | -6/+8 |
| 2017-01-04 | [AArch64] Add separate feature flag for weaker release consistent load insns | Szabolcs Nagy | 1 | -3/+8 |
| 2017-01-02 | Update year range in copyright notice of all files. | Alan Modra | 1 | -1/+1 |
| 2016-12-13 | [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm field | Renlin Li | 1 | -6/+6 |
| 2016-11-18 | [AArch64] Add ARMv8.3 FCMLA and FCADD instructions | Szabolcs Nagy | 1 | -0/+30 |
| 2016-11-18 | [AArch64] Add ARMv8.3 weaker release consistency load instructions | Szabolcs Nagy | 1 | -0/+3 |
| 2016-11-18 | [AArch64] Add ARMv8.3 javascript floating-point conversion instruction | Szabolcs Nagy | 1 | -0/+10 |
| 2016-11-18 | [AArch64] Add ARMv8.3 combined pointer authentication load instructions | Szabolcs Nagy | 1 | -0/+11 |
| 2016-11-11 | [AArch64] Add ARMv8.3 combined pointer authentication branch instructions | Szabolcs Nagy | 1 | -0/+12 |
| 2016-11-11 | [AArch64] Add ARMv8.3 PACGA instruction | Szabolcs Nagy | 1 | -0/+3 |
| 2016-11-11 | [AArch64] Add ARMv8.3 single source PAC instructions | Szabolcs Nagy | 1 | -0/+18 |
| 2016-11-11 | [AArch64] Add ARMv8.3 instructions which are in the NOP space | Szabolcs Nagy | 1 | -0/+18 |
| 2016-09-30 | [AArch64] PR target/20553, fix opcode mask for SIMD multiply by element | Jiong Wang | 1 | -4/+4 |
| 2016-09-21 | [AArch64][SVE 31/32] Add SVE instructions | Richard Sandiford | 1 | -0/+1269 |
| 2016-09-21 | [AArch64][SVE 29/32] Add new SVE core & FP register operands | Richard Sandiford | 1 | -0/+8 |
| 2016-09-21 | [AArch64][SVE 28/32] Add SVE FP immediate operands | Richard Sandiford | 1 | -0/+8 |
| 2016-09-21 | [AArch64][SVE 27/32] Add SVE integer immediate operands | Richard Sandiford | 1 | -0/+39 |
| 2016-09-21 | [AArch64][SVE 26/32] Add SVE MUL VL addressing modes | Richard Sandiford | 1 | -0/+18 |
| 2016-09-21 | [AArch64][SVE 25/32] Add support for SVE addressing modes | Richard Sandiford | 1 | -1/+88 |
| 2016-09-21 | [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED | Richard Sandiford | 1 | -0/+2 |
| 2016-09-21 | [AArch64][SVE 23/32] Add SVE pattern and prfop operands | Richard Sandiford | 1 | -0/+4 |
