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path: root/opcodes/aarch64-tbl.h
AgeCommit message (Expand)AuthorFilesLines
2023-06-28aarch64: Remove version dependencies from featuresAndrew Carlotti1-17/+19
2023-03-30aarch64: Add the RPRFM instructionRichard Sandiford1-0/+11
2023-03-30aarch64: Add the SVE FCLAMP instructionRichard Sandiford1-0/+1
2023-03-30aarch64: Add new SVE shift instructionsRichard Sandiford1-0/+3
2023-03-30aarch64: Add new SVE saturating conversion instructionsRichard Sandiford1-0/+3
2023-03-30aarch64: Add new SVE dot-product instructionsRichard Sandiford1-3/+12
2023-03-30aarch64: Add the SVE BFMLSL instructionsRichard Sandiford1-0/+7
2023-03-30aarch64: Add the SME2 UZP and ZIP instructionsRichard Sandiford1-0/+12
2023-03-30aarch64: Add the SME2 UNPK instructionsRichard Sandiford1-0/+4
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford1-0/+22
2023-03-30aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford1-0/+14
2023-03-30aarch64: Add the SME2 FP<->FP conversion instructionsRichard Sandiford1-0/+8
2023-03-30aarch64: Add the SME2 FP<->int conversion instructionsRichard Sandiford1-0/+20
2023-03-30aarch64: Add the SME2 CLAMP instructionsRichard Sandiford1-0/+6
2023-03-30aarch64: Add the SME2 MOPA and MOPS instructionsRichard Sandiford1-0/+6
2023-03-30aarch64: Add the SME2 vertical dot-product instructionsRichard Sandiford1-0/+10
2023-03-30aarch64: Add the SME2 dot-product instructionsRichard Sandiford1-0/+50
2023-03-30aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford1-0/+82
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford1-0/+74
2023-03-30aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford1-0/+28
2023-03-30aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford1-0/+44
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford1-0/+20
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford1-0/+42
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford1-0/+60
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford1-0/+136
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford1-0/+43
2023-03-30aarch64: Add support for predicate-as-counter registersRichard Sandiford1-0/+13
2023-03-30aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford1-3/+3
2023-03-30aarch64: Add a _10 suffix to FLD_imm3Richard Sandiford1-1/+1
2023-03-30aarch64: Regularise FLD_* suffixesRichard Sandiford1-16/+16
2023-03-30aarch64: Reorder some OP_SVE_* macrosRichard Sandiford1-16/+16
2023-03-30aarch64: Rename aarch64-tbl.h OP_SME_* macrosRichard Sandiford1-81/+77
2023-03-30aarch64: Add an operand class for SVE register listsRichard Sandiford1-2/+2
2023-03-30aarch64: Move ZA range checks to aarch64-opc.cRichard Sandiford1-21/+18
2023-03-30aarch64: Treat ZA as a registerRichard Sandiford1-1/+1
2023-03-30aarch64: Make SME instructions use F_STRICTRichard Sandiford1-9/+9
2023-03-30aarch64: Fix PSEL opcode maskRichard Sandiford1-1/+1
2023-03-30aarch64: Add sme-i16i64 and sme-f64f64 aliasesRichard Sandiford1-22/+22
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-11-14aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira1-1/+25
2022-10-17Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}CaiJingtao1-6/+15
2022-10-05Arm64: support CLEARBHB aliasJan Beulich1-0/+1
2022-01-06aarch64: Add support for new SME instructionsRichard Sandiford1-0/+3
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-12-02aarch64: Add BC instructionRichard Sandiford1-0/+7
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford1-6/+14
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-1/+106
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus1-0/+19
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus1-0/+8
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus1-0/+46
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