| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-01-25 | AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension. | Sudi Das | 1 | -1248/+1259 |
| 2019-01-25 | AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte... | Sudi Das | 1 | -1305/+1281 |
| 2019-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2018-11-12 | [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 1 | -1281/+1305 |
| 2018-11-12 | [BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 1 | -1275/+1286 |
| 2018-11-12 | [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten... | Sudakshina Das | 1 | -1416/+1528 |
| 2018-11-12 | [BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory Taggin... | Sudakshina Das | 1 | -1514/+1538 |
| 2018-11-12 | [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex... | Sudakshina Das | 1 | -2323/+2351 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction | Sudakshina Das | 1 | -973/+975 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions | Sudakshina Das | 1 | -946/+950 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A | Sudakshina Das | 1 | -913/+914 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A | Sudakshina Das | 1 | -2125/+2215 |
| 2018-07-12 | This patch adds support for the SSBB and PSSBB speculation barrier instructio... | Nick Clifton | 1 | -903/+906 |
| 2018-06-29 | Fix AArch64 encodings for by element instructions. | Tamar Christina | 1 | -69/+70 |
| 2018-06-22 | Correct negs aliasing on AArch64. | Tamar Christina | 1 | -3/+3 |
| 2018-05-16 | Fix disassembly mask for vector sdot on AArch64. | Tamar Christina | 1 | -158/+178 |
| 2018-05-15 | Modify AArch64 Assembly and disassembly functions to be able to fail and repo... | Tamar Christina | 1 | -62/+63 |
| 2018-03-28 | Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R... | Nick Clifton | 1 | -515/+548 |
| 2018-01-09 | Add support for the AArch64's CSDB instruction. | James Greenhalgh | 1 | -899/+900 |
| 2018-01-03 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2017-11-16 | Add assembler and disassembler support for the new Armv8.4-a instructions for... | Tamar Christina | 1 | -2924/+3464 |
| 2017-11-09 | Adds the new Fields and Operand types for the new instructions in Armv8.4-a. | Tamar Christina | 1 | -89/+95 |
| 2017-07-24 | [AArch64] Fix the bit pattern order in the comments in auto-generated file | Jiong Wang | 1 | -1686/+1686 |
| 2017-06-28 | [AArch64] Add dot product support for AArch64 to binutils | Tamar Christina | 1 | -179/+203 |
| 2017-02-24 | [AArch64] Additional SVE instructions | Richard Sandiford | 1 | -1856/+2294 |
| 2017-01-02 | Update year range in copyright notice of all files. | Alan Modra | 1 | -1/+1 |
| 2016-12-13 | [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm field | Renlin Li | 1 | -2/+2 |
| 2016-11-18 | [AArch64] Add ARMv8.3 FCMLA and FCADD instructions | Szabolcs Nagy | 1 | -2121/+2158 |
| 2016-11-18 | [AArch64] Add ARMv8.3 weaker release consistency load instructions | Szabolcs Nagy | 1 | -1151/+1184 |
| 2016-11-18 | [AArch64] Add ARMv8.3 javascript floating-point conversion instruction | Szabolcs Nagy | 1 | -1270/+1281 |
| 2016-11-18 | [AArch64] Add ARMv8.3 combined pointer authentication load instructions | Szabolcs Nagy | 1 | -1197/+1221 |
| 2016-11-11 | [AArch64] Add ARMv8.3 combined pointer authentication branch instructions | Szabolcs Nagy | 1 | -1508/+1640 |
| 2016-11-11 | [AArch64] Add ARMv8.3 PACGA instruction | Szabolcs Nagy | 1 | -1430/+1442 |
| 2016-11-11 | [AArch64] Add ARMv8.3 single source PAC instructions | Szabolcs Nagy | 1 | -1442/+1640 |
| 2016-11-11 | [AArch64] Add ARMv8.3 instructions which are in the NOP space | Szabolcs Nagy | 1 | -786/+799 |
| 2016-09-21 | [AArch64][SVE 31/32] Add SVE instructions | Richard Sandiford | 1 | -115/+7931 |
| 2016-09-21 | [AArch64][SVE 29/32] Add new SVE core & FP register operands | Richard Sandiford | 1 | -10/+16 |
| 2016-09-21 | [AArch64][SVE 28/32] Add SVE FP immediate operands | Richard Sandiford | 1 | -25/+32 |
| 2016-09-21 | [AArch64][SVE 27/32] Add SVE integer immediate operands | Richard Sandiford | 1 | -38/+62 |
| 2016-09-21 | [AArch64][SVE 26/32] Add SVE MUL VL addressing modes | Richard Sandiford | 1 | -18/+27 |
| 2016-09-21 | [AArch64][SVE 25/32] Add support for SVE addressing modes | Richard Sandiford | 1 | -19/+57 |
| 2016-09-21 | [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED | Richard Sandiford | 1 | -6/+8 |
| 2016-09-21 | [AArch64][SVE 23/32] Add SVE pattern and prfop operands | Richard Sandiford | 1 | -5/+7 |
| 2016-09-21 | [AArch64][SVE 21/32] Add Zn and Pn registers | Richard Sandiford | 1 | -0/+20 |
| 2016-09-21 | [AArch64][SVE 16/32] Use specific insert/extract methods for fpimm | Richard Sandiford | 1 | -1/+2 |
| 2016-01-01 | Copyright update for binutils | Alan Modra | 1 | -1/+1 |
| 2015-12-14 | [AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru... | Matthew Wahab | 1 | -674/+682 |
| 2015-12-14 | [AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions. | Matthew Wahab | 1 | -898/+903 |
| 2015-12-14 | [AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions. | Matthew Wahab | 1 | -754/+809 |
| 2015-12-14 | [AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions. | Matthew Wahab | 1 | -1154/+1156 |
