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AgeCommit message (Expand)AuthorFilesLines
2020-02-19RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson1-0/+5
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu1-0/+14
2020-02-17x86: fold certain VCVT{,U}SI2S{S,D} templatesJan Beulich1-0/+7
2020-02-17x86: fold AddrPrefixOpReg templatesJan Beulich1-0/+8
2020-02-17x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich1-0/+11
2020-02-16x86: Don't disable SSE3 when disabling SSE4aH.J. Lu1-0/+5
2020-02-17Re: x86: Don't disable SSE4a when disabling SSE4Alan Modra1-0/+4
2020-02-16x86: Don't disable SSE4a when disabling SSE4H.J. Lu1-0/+5
2020-02-14Remove Intel syntax comments on movsx and movzxH.J. Lu1-0/+5
2020-02-14x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich1-0/+8
2020-02-13x86: fix SSE4a dependencies of ".arch .nosse*"Jan Beulich1-0/+7
2020-02-12x86: correct VFPCLASSP{S,D} operand size handlingJan Beulich1-0/+6
2020-02-12x86: fold two JMP templatesJan Beulich1-0/+5
2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich1-0/+10
2020-02-11x86: drop ShortForm attributeJan Beulich1-0/+12
2020-02-11x86: drop stray ShortForm attributesJan Beulich1-0/+6
2020-02-11Ensure *valuep always written by extract_normal returnAlan Modra1-0/+8
2020-02-10[binutils][arm] Implement Custom Datapath Extensions for MVEMatthew Malcomson1-0/+5
2020-02-10[binutils][arm] arm support for ARMv8.m Custom Datapath ExtensionMatthew Malcomson1-0/+12
2020-02-10x86: Accept Intel64 only instruction by defaultH.J. Lu1-0/+18
2020-02-07Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add ...Sergey Belyashov1-0/+5
2020-02-04ubsan: d30v: negation of -2147483648Alan Modra1-0/+4
2020-02-03ubsan: m32c: left shift of negative valueAlan Modra1-0/+4
2020-02-01ubsan: frv: left shift of negative valueAlan Modra1-0/+4
2020-01-31x86: replace EXxmm_mdq by EXVexWdqScalarJan Beulich1-0/+8
2020-01-31x86: drop unused EXVexWdq / vex_w_dq_modeJan Beulich1-0/+7
2020-01-31aarch64: Fix MOVPRFX markup for bf16 conversionsRichard Sandiford1-0/+5
2020-01-30ubsan: m32c: left shift of negative valueAlan Modra1-0/+4
2020-01-30cpu,opcodes,gas: fix neg and neg32 instructions in BPFJose E. Marchesi1-0/+4
2020-01-30x86-64: honor vendor specifics for near RETJan Beulich1-0/+9
2020-01-30x86: drop further pointless/bogus DefaultSizeJan Beulich1-0/+8
2020-01-30ubsan: tic4x: left shift cannot be represented in type 'int'Alan Modra1-0/+4
2020-01-27x86-64: Properly encode and decode movsxdH.J. Lu1-0/+15
2020-01-27AArch64: Fix cfinv disassembly issuesTamar Christina1-0/+8
2020-01-21x86: improve handling of insns with ambiguous operand sizesJan Beulich1-0/+5
2020-01-21x86: VCVTNEPS2BF16{X,Y} should permit broadcastingJan Beulich1-0/+7
2020-01-20Updated translations for various binutils sub-directoriesNick Clifton1-0/+6
2020-01-20ubsan: hppa: negation of -2147483648Alan Modra1-0/+4
2020-01-20ubsan: arm: out of bounds array accessAlan Modra1-0/+4
2020-01-18Update version to 2.34.50. Regenerate configure and .pot files.Nick Clifton1-0/+5
2020-01-18Add markers for 2.34 branch to the NEWS files and ChangeLogs.Nick Clifton1-0/+4
2020-01-17Fix spelling errorsChristian Biesinger1-0/+4
2020-01-17x86: Add {vex} pseudo prefixH.J. Lu1-0/+5
2020-01-16[binutils][arm] PR25376 Change MVE into a CORE_HIGH featureAndre Vieira1-0/+9
2020-01-16x86: drop stale Vec_Imm4 related commentJan Beulich1-0/+4
2020-01-16x86: add a few more missing VexWIGJan Beulich1-0/+6
2020-01-16x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit modeJan Beulich1-0/+8
2020-01-16tic4x disassembly static variablesAlan Modra1-0/+10
2020-01-14Fix various assembler testsuite failures for the Z80 target.Sergey Belyashov1-0/+6
2020-01-14ubsan: z8k: left shift cannot be represented in type 'int'Alan Modra1-0/+5
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