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AgeCommit message (Expand)AuthorFilesLines
2020-06-14x86: Correct xsusldtrk mnemonicH.J. Lu1-0/+7
2020-06-12RISC-V: Drop the privileged spec v1.9 support.Nelson Chu1-0/+4
2020-06-11[PATCH]: aarch64: Refactor representation of system registersAlex Coplan1-0/+23
2020-06-09i386-dis.c: Fix a typo in commentsH.J. Lu1-0/+4
2020-06-09x86: consistently print prefixes explicitly which are invalid with VEX etcJan Beulich1-0/+8
2020-06-09x86: fix {,V}MOV{L,H}PD disassemblyJan Beulich1-0/+15
2020-06-09x86: utilize X macro in EVEX decodingJan Beulich1-0/+60
2020-06-09x86: correct decoding of packed-FP-only AVX encodingsJan Beulich1-0/+10
2020-06-09x86: correct mis-named MOD_0F51 enumeratorJan Beulich1-0/+5
2020-06-08[PATCH] arm: Add DFB instruction for ARMv8-RAlex Coplan1-0/+5
2020-06-08x86: restrict use of register aliasesJan Beulich1-0/+4
2020-06-06Power10 tidiesAlan Modra1-0/+4
2020-06-05bpf stack smashing detectedAlan Modra1-0/+5
2020-06-04cpu,gas,opcodes: remove no longer needed workaround from the BPF portJose E. Marchesi1-0/+8
2020-06-04opcodes: discriminate endianness and insn-endianness in CGEN portsJose E. Marchesi1-0/+43
2020-06-04opcodes: support insn endianness in cgen_cpu_openJose E. Marchesi1-0/+33
2020-06-03Updated Serbian translation for the opcodes sub-directoryNick Clifton1-0/+4
2020-06-03RISC-V: Fix the error when building RISC-V linux native gdbserver.Nelson Chu1-0/+5
2020-06-01Regen opcodes/bpf-desc.cAlan Modra1-0/+4
2020-05-28cpu,opcodes: add instruction semantics to bpf.cpu and minor fixesJose E. Marchesi1-0/+8
2020-05-28ubsan: nios2: undefined shiftAlan Modra1-0/+5
2020-05-28asan: ns32k: use of uninitialized valueAlan Modra1-0/+6
2020-05-28Fix a potential use of an uninitialised value in the ns32k disassembler.Nick Clifton1-0/+5
2020-05-26Fix extraction of signed constants in nios2 disassembler (again).Sandra Loosemore1-0/+7
2020-05-26ChangeLog entries for f687f5f563Stefan Schulze Frielinghaus1-0/+6
2020-05-21Replace "if (x) free (x)" with "free (x)", opcodesAlan Modra1-0/+22
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu1-0/+31
2020-05-19Power10 dcbf, sync, and wait extensions.Peter Bergner1-0/+17
2020-05-19or1k: Regenerate opcodes after removing 32-bit supportStafford Horne1-0/+12
2020-05-11Power10 VSX scalar min-max-compare quad precision operationsAlan Modra1-0/+5
2020-05-11Power10 VSX load/store rightmost element operationsAlan Modra1-0/+5
2020-05-11Power10 test lsb by byte operationAlan Modra1-0/+4
2020-05-11Power10 string operationsAlan Modra1-0/+5
2020-05-11Power10 Set boolean extensionPeter Bergner1-0/+5
2020-05-11Power10 bit manipulation operationsAlan Modra1-0/+7
2020-05-11Power10 VSX PCV generate operationsAlan Modra1-0/+5
2020-05-11Power10 VSX Mask Manipulation OperationsAlan Modra1-0/+9
2020-05-11Power10 Reduced precision outer product operationsAlan Modra1-0/+25
2020-05-11Power10 SIMD permute class operationsAlan Modra1-0/+15
2020-05-11Power10 128-bit binary integer operationsAlan Modra1-0/+8
2020-05-11Power10 VSX 32-byte storage accessAlan Modra1-0/+7
2020-05-11Power10 vector integer multiply, divide, modulo insnsAlan Modra1-0/+6
2020-05-11Power10 byte reverse instructionsPeter Bergner1-0/+4
2020-05-11Power10 Copy/Paste ExtensionsPeter Bergner1-0/+6
2020-05-11Power10 Add new L operand to the slbiag instructionPeter Bergner1-0/+4
2020-05-11PowerPC Default disassembler to -Mpower10Alan Modra1-0/+4
2020-05-11PowerPC Rename powerxx to power10Alan Modra1-0/+6
2020-05-11Updated French translation for the ld sub-directory and an update Spanish tra...Nick Clifton1-0/+4
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan1-0/+12
2020-04-29Also use unsigned 8-bit immediate values for the LDRC and SETRC insns.Nick Clifton1-0/+6
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