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AgeCommit message (Expand)AuthorFilesLines
2020-05-28Fix a potential use of an uninitialised value in the ns32k disassembler.Nick Clifton1-0/+5
2020-05-26Fix extraction of signed constants in nios2 disassembler (again).Sandra Loosemore1-0/+7
2020-05-26ChangeLog entries for f687f5f563Stefan Schulze Frielinghaus1-0/+6
2020-05-21Replace "if (x) free (x)" with "free (x)", opcodesAlan Modra1-0/+22
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu1-0/+31
2020-05-19Power10 dcbf, sync, and wait extensions.Peter Bergner1-0/+17
2020-05-19or1k: Regenerate opcodes after removing 32-bit supportStafford Horne1-0/+12
2020-05-11Power10 VSX scalar min-max-compare quad precision operationsAlan Modra1-0/+5
2020-05-11Power10 VSX load/store rightmost element operationsAlan Modra1-0/+5
2020-05-11Power10 test lsb by byte operationAlan Modra1-0/+4
2020-05-11Power10 string operationsAlan Modra1-0/+5
2020-05-11Power10 Set boolean extensionPeter Bergner1-0/+5
2020-05-11Power10 bit manipulation operationsAlan Modra1-0/+7
2020-05-11Power10 VSX PCV generate operationsAlan Modra1-0/+5
2020-05-11Power10 VSX Mask Manipulation OperationsAlan Modra1-0/+9
2020-05-11Power10 Reduced precision outer product operationsAlan Modra1-0/+25
2020-05-11Power10 SIMD permute class operationsAlan Modra1-0/+15
2020-05-11Power10 128-bit binary integer operationsAlan Modra1-0/+8
2020-05-11Power10 VSX 32-byte storage accessAlan Modra1-0/+7
2020-05-11Power10 vector integer multiply, divide, modulo insnsAlan Modra1-0/+6
2020-05-11Power10 byte reverse instructionsPeter Bergner1-0/+4
2020-05-11Power10 Copy/Paste ExtensionsPeter Bergner1-0/+6
2020-05-11Power10 Add new L operand to the slbiag instructionPeter Bergner1-0/+4
2020-05-11PowerPC Default disassembler to -Mpower10Alan Modra1-0/+4
2020-05-11PowerPC Rename powerxx to power10Alan Modra1-0/+6
2020-05-11Updated French translation for the ld sub-directory and an update Spanish tra...Nick Clifton1-0/+4
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan1-0/+12
2020-04-29Also use unsigned 8-bit immediate values for the LDRC and SETRC insns.Nick Clifton1-0/+6
2020-04-29Updated Serbian translation for the binutils sub-directory, and Swedish trans...Nick Clifton1-0/+4
2020-04-29Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate ...Nick Clifton1-0/+8
2020-04-21Disallow PC relative for CMPI on MC68000/10Andreas Schwab1-0/+6
2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das1-0/+15
2020-04-20[AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das1-0/+12
2020-04-17[PATCH v2] binutils: arm: Fix disassembly of conditional VDUPs.Fredrik Strupe1-0/+6
2020-04-16cpu,gas,opcodes: support for eBPF JMP32 instruction classDavid Faust1-0/+7
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili1-0/+14
2020-04-02Add support for intel SERIALIZE instructionLiliCui1-0/+12
2020-03-26Re: H8300 use of uninitialised valueAlan Modra1-0/+13
2020-03-26Re: ARC: Use of uninitialised valueAlan Modra1-0/+4
2020-03-25Uninitialised memory read in z80-dis.cAlan Modra1-0/+4
2020-03-22H8300 use of uninitialised valueAlan Modra1-0/+5
2020-03-22ARC: Use of uninitialised valueAlan Modra1-0/+6
2020-03-22NS32K arg_bufs uninitialisedAlan Modra1-0/+7
2020-03-22s12z disassembler tidyAlan Modra1-0/+31
2020-03-20metag uninitialized memory readAlan Modra1-0/+5
2020-03-20NDS32 disassembly of odd sized sectionsAlan Modra1-0/+7
2020-03-20PowerPC disassembly of odd sized sectionsAlan Modra1-0/+7
2020-03-17Replace a couple of assertions in the BFD library that can be triggered by at...Nick Clifton1-0/+5
2020-03-13x86-64: correct mis-named X86_64_0D enumeratorJan Beulich1-0/+5
2020-03-09x86: Also pass -P to $(CPP) when processing i386-opc.tblH.J. Lu1-0/+5
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