aboutsummaryrefslogtreecommitdiff
path: root/opcodes/ChangeLog
AgeCommit message (Expand)AuthorFilesLines
2018-03-22x86: drop pointless VecESizeJan Beulich1-0/+6
2018-03-22x86: drop remaining redundant DispNJan Beulich1-0/+6
2018-03-22x86: fix swapped operand handling for BNDMOVJan Beulich1-0/+8
2018-03-22x86/Intel: fix fallout from earlier template foldingJan Beulich1-0/+7
2018-03-22x86: fold a few XOP templatesJan Beulich1-0/+6
2018-03-14RISC-V: Add .insn support.Jim Wilson1-0/+4
2018-03-13Updated Russian and Brazilian Portuguese translations.Nick Clifton1-0/+4
2018-03-08x86-64: Also optimize "clr reg64"H.J. Lu1-0/+5
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu1-0/+9
2018-03-08x86: fold several AVX512VL templatesJan Beulich1-0/+6
2018-03-08x86: fold certain AVX512 rotate and shift templatesJan Beulich1-0/+7
2018-03-08x86: fold VEX-encoded GFNI templatesJan Beulich1-0/+6
2018-03-08x86: fold a few AVX512F templatesJan Beulich1-0/+7
2018-03-08x86: fold LWP templatesJan Beulich1-0/+6
2018-03-08x86: fold FMA and FMA4 templatesJan Beulich1-0/+6
2018-03-08x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich1-0/+5
2018-03-08x86: drop bogus NoAVXJan Beulich1-0/+6
2018-03-08x86: avoid SSE check for LDMXCSR/STMXCSRJan Beulich1-0/+5
2018-03-08x86: drop FloatDJan Beulich1-0/+9
2018-03-08x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich1-0/+4
2018-03-08x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich1-0/+5
2018-03-08x86: fold AVX vcvtpd2ps memory formsJan Beulich1-0/+6
2018-03-07XCOFF disassemblerAlan Modra1-0/+9
2018-03-03opcodes error messagesAlan Modra1-0/+31
2018-03-01x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu1-0/+6
2018-03-01Add missing translations to ALL_LINGUASAlan Modra1-0/+5
2018-02-27[ARM] Remove ARM_FEATURE_COPY macroThomas Preud'homme1-0/+5
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu1-0/+14
2018-02-26crx string overflow warningAlan Modra1-0/+5
2018-02-22RISC-V: Make disassebler work for --enable-targets=all config.Jim Wilson1-0/+4
2018-02-22x86: Add {rex} pseudo prefixH.J. Lu1-0/+5
2018-02-20MIPS16/opcodes: Free up `M' operand codeMaciej W. Rozycki1-0/+5
2018-02-19[ARM] Fix bxns maskThomas Preud'homme1-0/+4
2018-02-13Fix compile time warning messages from gcc version 8 about cast between incom...Nick Clifton1-0/+6
2018-02-13WebAssembly: Correct an `index' global shadowing error for pre-4.8 GCCMaciej W. Rozycki1-0/+5
2018-02-12MIPS: Fix encoding for MIPSr6 sigrie instruction.Henry Wong1-0/+4
2018-02-05Updated Brazillian portuguese and Russian translationNick Clifton1-0/+4
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist1-0/+11
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist1-0/+11
2018-01-17RISC-V: Fix bug in prior addi/c.nop patch.Jim Wilson1-0/+4
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist1-0/+12
2018-01-16Update translations for various binutils components.Nick Clifton1-0/+5
2018-01-15RISC-V: Add support for addi that compresses to c.nop.Jim Wilson1-0/+5
2018-01-15Update Ukranian translations for bfd, binutils, gas, gold, ld and opcodesNick Clifton1-0/+4
2018-01-13Update pot filesNick Clifton1-0/+4
2018-01-13Bump version number to 2.30.51Nick Clifton1-0/+4
2018-01-13Add note about 2.30 branch creation to changelogsNick Clifton1-0/+4
2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist1-0/+5
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich1-0/+5
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich1-0/+10
generated by cgit v1.1 at 2025-03-05 04:45:39 +0000